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drivers: i3c: Support I3C driver for STM32. #81190
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drivers: i3c: Support I3C driver for STM32. #81190
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i3c_shell.c
also needs updated
zephyr/drivers/i3c/i3c_shell.c
Line 82 in c50777a
DT_FOREACH_STATUS_OKAY(cdns_i3c, I3C_CTRL_FN) |
and
zephyr/drivers/i3c/i3c_shell.c
Line 96 in c50777a
DT_FOREACH_STATUS_OKAY(cdns_i3c, I3C_CTRL_LIST_ENTRY) |
@ExaltZephyr You should put your legal name in |
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Merge commit should be dropped.
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The title of each commit should reflect the path of where changes are introduced, see the main branch for examples.
Still not fixed. Without this your PR cannot be merged. |
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About Sign-off (
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drivers/i3c/i3c_stm32.c
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LL_I3C_SetDataHoldTime(i3c, LL_I3C_SDA_HOLD_TIME_1_5); | ||
LL_I3C_SetFreeTiming(i3c, free_timing); | ||
LL_I3C_SetControllerActivityState(i3c, LL_I3C_OWN_ACTIVITY_STATE_0); |
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this appears to be set in multiple places, it probably should be only set once in the init
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not resolved!!, this probably should be within i3c_stm32_controller_init
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In this section, I calculate the free_timing value based on specific calculations and use it with LL_I3C_SetFreeTiming. The functions LL_I3C_SetDataHoldTime and LL_I3C_SetControllerActivityState are included alongside LL_I3C_SetFreeTiming as they all modify the same register.
ok ?
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I'm only referring to LL_I3C_SetControllerActivityState
here but this is modifying the value it could receive from the active controller through the ENTAS# CCC. It shouldn't be modified with every call to configure
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/* After receiving all bytes for current target, move on to the next target | ||
*/ | ||
if (target->num_xfer == target->data_len) { |
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A target can send an EoD when doing a read with a CCC and it's possible for the num_xfer to be less than the data_len. This can happen with variable length CCCs such as GETCAPS and GETMXDS. Does this handle this situation?
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No it is not handled, we are currently thinking of a way to handle this issue. The problem is that the information about the target early read termination can be obtained from the status FIFO, however, we might be receiving data from the next target before the data from the status FIFO is ready.
One suggestion we are thinking of is to disable the status FIFO for CCC requests and rely on the RXTGTENDF interrupt to detect early target termination and advance the ccc_target_payload
pointer.
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Please do not resolve comments on your own, and let the original poster do it instead. |
This commit adds the main DTS configurations required to enable I3C support on STM32. Signed-off-by: Mohammad Badawi <[email protected]> Signed-off-by: Sara Touqan <[email protected]>
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This commit introduces support for the I3C driver on STM32, enabling functionality APIs for I3C controllers. Signed-off-by: Mohammad Badawi <[email protected]> Signed-off-by: Sara Touqan <[email protected]>
This commit introduces support for I3C shell on STM32. Signed-off-by: Mohammad Badawi <[email protected]> Signed-off-by: Sara Touqan <[email protected]>
This commit enables I3C support for STM32 nucleo_h563zi boards. Signed-off-by: Mohammad Badawi <[email protected]> Signed-off-by: Sara Touqan <[email protected]>
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This PR introduces support for the I3C driver on STM32, enabling functionality APIs for I3C controllers.