drivers: i3c: Support I3C driver for STM32.

This commit introduces support for the I3C driver on STM32, enabling functionality APIs for I3C controllers. Signed-off-by: ExaltZephyr <[email protected]>
zephyrproject-rtos · Nov 11, 2024 · 9ddd65f · 9ddd65f
1 parent 4c02ce1
commit 9ddd65f
Showing 1 changed file with 36 additions and 36 deletions.
diff --git a/dts/bindings/i3c/st,stm32-i3c.yaml b/dts/bindings/i3c/st,stm32-i3c.yaml
@@ -9,39 +9,39 @@ compatible: "st,stm32-i3c"
 include: [i3c-controller.yaml, pinctrl-device.yaml]
 
 properties:
-	reg:
-		required: true
-
-	interrupts:
-		required: true
-
-	pinctrl-names:
-		required: true
-
-	dmas:
-		description: |
-			Optional DMA channel specifier, required for DMA transactions.
-			For example dmas for TX/RX/TC/RS on I3C
-					dmas = <&gpdma1 0 120 STM32_DMA_PERIPH_RX
-					&gpdma1 1 121 STM32_DMA_PERIPH_TX
-					&gpdma1 2 122 (STM32_DMA_PERIPH_TX | STM32_DMA_MEM_32BITS | STM32_DMA_PERIPH_32BITS)
-					&gpdma1 3 123 (STM32_DMA_PERIPH_RX | STM32_DMA_MEM_32BITS | STM32_DMA_PERIPH_32BITS)>;
-
-			With, in each cell of the dmas specifier:
-			- &gpdma1: dma controller phandle
-			- 0: channel number (0 to Max-Channel minus 1). From 0 to 7 on stm32h5x.
-			- 120: slot number (request which could be given by the GPDMA)
-			- STM32_DMA_PERIPH_RX: channel configuration (only for srce/dest data size, priority)
-
-			For example dmas for TX/RX/TC/RS on I3C
-					dmas = <&gpdma1 0 120 STM32_DMA_PERIPH_RX
-					&gpdma1 1 121 STM32_DMA_PERIPH_TX
-					&gpdma1 2 122 (STM32_DMA_PERIPH_TX | STM32_DMA_MEM_32BITS | STM32_DMA_PERIPH_32BITS)
-					&gpdma1 3 123 (STM32_DMA_PERIPH_RX | STM32_DMA_MEM_32BITS | STM32_DMA_PERIPH_32BITS)>;
-
-	dma-names:
-		description: |
-			DMA channel name. If DMA should be used, expected value is "rx" "tx" "tc" "rs".
-
-			For example
-				 dma-names = "rx", "tx", "tc", "rs";
+  reg:
+    required: true
+
+  interrupts:
+    required: true
+
+  pinctrl-names:
+    required: true
+
+  dmas:
+    description: |
+      Optional DMA channel specifier, required for DMA transactions.
+      For example dmas for TX/RX/TC/RS on I3C
+         	dmas = <&gpdma1 0 120 STM32_DMA_PERIPH_RX
+          &gpdma1 1 121 STM32_DMA_PERIPH_TX
+          &gpdma1 2 122 (STM32_DMA_PERIPH_TX | STM32_DMA_MEM_32BITS | STM32_DMA_PERIPH_32BITS)
+          &gpdma1 3 123 (STM32_DMA_PERIPH_RX | STM32_DMA_MEM_32BITS | STM32_DMA_PERIPH_32BITS)>;
+
+      With, in each cell of the dmas specifier:
+      - &gpdma1: dma controller phandle
+      - 0: channel number (0 to Max-Channel minus 1). From 0 to 7 on stm32h5x.
+      - 120: slot number (request which could be given by the GPDMA)
+      - STM32_DMA_PERIPH_RX: channel configuration (only for srce/dest data size, priority)
+
+      For example dmas for TX/RX/TC/RS on I3C
+          dmas = <&gpdma1 0 120 STM32_DMA_PERIPH_RX
+          &gpdma1 1 121 STM32_DMA_PERIPH_TX
+          &gpdma1 2 122 (STM32_DMA_PERIPH_TX | STM32_DMA_MEM_32BITS | STM32_DMA_PERIPH_32BITS)
+          &gpdma1 3 123 (STM32_DMA_PERIPH_RX | STM32_DMA_MEM_32BITS | STM32_DMA_PERIPH_32BITS)>;
+
+  dma-names:
+    description: |
+      DMA channel name. If DMA should be used, expected value is "rx" "tx" "tc" "rs".
+
+      For example
+         dma-names = "rx", "tx", "tc", "rs";