drivers: i3c: Fix issues with check_patch and check_compliance checks.

Addressed issues in the I3C driver related to the check_patch and check_compliance functions to ensure proper functionality and alignment with coding standards. Signed-off-by: ExaltZephyr <[email protected]>
zephyrproject-rtos · Nov 11, 2024 · 4c02ce1 · 4c02ce1
1 parent c962cfa
commit 4c02ce1
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diff --git a/boards/st/nucleo_h563zi/nucleo_h563zi-common.dtsi b/boards/st/nucleo_h563zi/nucleo_h563zi-common.dtsi
@@ -79,10 +79,10 @@
 };
 
 &i3c1 {
-    pinctrl-0 =  <&i3c1_scl_pd12 &i3c1_sda_pd13>;
-    i3c-scl-hz = <12500000>;
-    i2c-scl-hz = <400000>;
-    status = "okay";
+	pinctrl-0 =  <&i3c1_scl_pd12 &i3c1_sda_pd13>;
+	i3c-scl-hz = <12500000>;
+	i2c-scl-hz = <400000>;
+	status = "okay";
 };
 
 &rcc {

diff --git a/drivers/i3c/Kconfig.stm32 b/drivers/i3c/Kconfig.stm32
@@ -8,34 +8,34 @@ module-str = i3c_stm32
 
 source "subsys/logging/Kconfig.template.log_config"
 config I3C_STM32
-    bool "STM32 I3C driver support"
-    depends on DT_HAS_ST_STM32_I3C_ENABLED
-    select USE_STM32_HAL_I3C
-    default y
-    help
-      Enable support for I3C on STM32 microcontrollers.
+		bool "STM32 I3C driver support"
+		depends on DT_HAS_ST_STM32_I3C_ENABLED
+		select USE_STM32_HAL_I3C
+		default y
+		help
+			Enable support for I3C on STM32 microcontrollers.
 
 config I3C_STM32_POLL
-    bool "Enables I3C polling mode"
-    depends on I3C_STM32
-    default n
-    help
-      Enables polling mode for I3C on STM32 microcontrollers.
+		bool "I3C polling mode for STM32"
+		depends on I3C_STM32
+		default n
+		help
+			Enables polling mode for I3C on STM32 microcontrollers.
 
 config I3C_STM32_DMA
-    bool "STM32 I3C DMA driver support"
-    depends on I3C_STM32 && DMA_STM32U5 && !I3C_STM32_POLL
-    help
-      Enables support for I3C DMA mode on STM32 microcontrollers.
-      This option is incompatible with I3C_STM32_POLL
+		bool "STM32 I3C DMA driver support"
+		depends on I3C_STM32 && DMA_STM32U5 && !I3C_STM32_POLL
+		help
+			Enables support for I3C DMA mode on STM32 microcontrollers.
+			This option is incompatible with I3C_STM32_POLL
 
 config I3C_STM32_DMA_FIFO_HEAP_SIZE
-    int "Status FIFO and control FIFO heap"
-    depends on I3C_STM32_DMA
-    default 2048
-    help
-      Configures the heap size for dynamically allocating the regions for
-      storing status FIFO and control FIFO words which will be used by the DMA.
-      This value depends on the maximum number of messages that will be sent
-      during a single transfer. 2KB guarantees enough heap size for sending 256
-      messages on a single transfer.
+		int "Status FIFO and control FIFO heap"
+		depends on I3C_STM32_DMA
+		default 2048
+		help
+			Configures the heap size for dynamically allocating the regions for
+			storing status FIFO and control FIFO words which will be used by the DMA.
+			This value depends on the maximum number of messages that will be sent
+			during a single transfer. 2KB guarantees enough heap size for sending 256
+			messages on a single transfer.
diff --git a/drivers/i3c/i3c_stm32.c b/drivers/i3c/i3c_stm32.c
@@ -94,7 +94,7 @@ struct i3c_stm32_dma_stream {
 struct i3c_stm32_msg {
 	uint8_t target_addr;         /* Current target xfer address */
 	struct i3c_msg *i3c_msg_ptr; /* Pointer to the current private message to send on the bus */
-	struct i3c_msg *i3c_msg_ctrl_ptr;   /* Pointer to the private message that will be used by the control FIFO */
+	struct i3c_msg *i3c_msg_ctrl_ptr; /* Pointer to the private message that will be used by the control FIFO */
 	struct i3c_msg *i3c_msg_status_ptr; /* Pointer to the private message that will be used by the status FIFO */
 	struct i2c_msg *i2c_msg_ptr; /* Pointer to the current legacy message to send on the bus */
 	struct i2c_msg *i2c_msg_ctrl_ptr; /* Pointer to the I2C legavy message that will be used by the control FIFO */
@@ -119,10 +119,8 @@ struct i3c_stm32_data {
 	enum i3c_stm32_msg_state msg_state;  /* Current I3C bus state */
 	enum i3c_stm32_sf_state sf_state;    /* Current I3C status FIFO state */
 	struct i3c_ccc_payload *ccc_payload; /* Current CCC message payload */
-	struct i3c_ccc_target_payload *
-		ccc_target_payload;              /* Current target addressed by 2nd part of direct CCC command */
-	struct i3c_ccc_target_payload
-		*ccc_target_payload_sf;          /* Current target addressed by 2nd part of direct CCC command used by the status FIFO */
+	struct i3c_ccc_target_payload *ccc_target_payload; /* Current target addressed by 2nd part of direct CCC command */
+	struct i3c_ccc_target_payload *ccc_target_payload_sf; /* Current target addressed by 2nd part of direct CCC command used by the status FIFO */
 	size_t ccc_target_idx;          /* Current target index, used for filling C-FIFO */
 	struct k_sem device_sync_sem;   /* Sync between device communication messages */
 	struct k_sem bus_mutex;         /* Sync between transfers */
@@ -781,7 +779,7 @@ static void i3c_stm32_clear_err(const struct device *dev, bool is_i2c_xfer)
  * @return Returns true if last byte was sent (TXLAST flag was set)
  */
 static bool i3c_stm32_fill_tx_fifo(const struct device *dev, uint8_t *buf, size_t len,
-				     size_t *offset)
+				   size_t *offset)
 {
 	const struct i3c_stm32_config *config = dev->config;
 	I3C_TypeDef *i3c = config->i3c;
@@ -819,7 +817,7 @@ static bool i3c_stm32_fill_tx_fifo(const struct device *dev, uint8_t *buf, size_
  * @return Returns true if last byte was received (RXLAST flag was set)
  */
 static bool i3c_stm32_drain_rx_fifo(const struct device *dev, uint8_t *buf, uint32_t len,
-				      size_t *offset)
+				    size_t *offset)
 {
 	const struct i3c_stm32_config *config = dev->config;
 	I3C_TypeDef *i3c = config->i3c;
@@ -1273,16 +1271,15 @@ static int i3c_stm32_dma_msg_config(const struct device *dev, uint32_t buf_addr,
 	int ret;
 
 	if (i3c_stm32_curr_msg_xfer_is_read(dev)) {
-		dma_stream =  &(data->dma_rx);
+		dma_stream = &(data->dma_rx);
 		dma_stream->blk_cfg.dest_address = buf_addr;
 	} else {
-		dma_stream =  &(data->dma_tx);
+		dma_stream = &(data->dma_tx);
 		dma_stream->blk_cfg.source_address = buf_addr;
 	}
 
 	dma_stream->blk_cfg.block_size = buf_len;
-	ret = dma_config(dma_stream->dma_dev, dma_stream->dma_channel,
-				&dma_stream->dma_cfg);
+	ret = dma_config(dma_stream->dma_dev, dma_stream->dma_channel, &dma_stream->dma_cfg);
 
 	if (ret != 0) {
 		LOG_ERR("TX/RX DMA config error, err=%d", ret);
@@ -1476,9 +1473,9 @@ static int i3c_stm32_transfer_begin(const struct device *dev)
 	data->msg_state = STM32_I3C_MSG;
 	data->sf_state = STM32_I3C_SF;
 
-	#ifdef CONFIG_PM_DEVICE_RUNTIME
-		(void)pm_device_runtime_get(dev);
-	#endif
+#ifdef CONFIG_PM_DEVICE_RUNTIME
+	(void)pm_device_runtime_get(dev);
+#endif
 
 	/* Prevent the clocks to be stopped during the transaction */
 	pm_policy_state_lock_get(PM_STATE_SUSPEND_TO_IDLE, PM_ALL_SUBSTATES);
@@ -1692,7 +1689,8 @@ static int i3c_stm32_pm_action(const struct device *dev, enum pm_device_action a
 
 #ifdef CONFIG_I3C_STM32_DMA
 static int i3c_stm32_dma_stream_config(const struct device *dev,
-		struct i3c_stm32_dma_stream *dma_stream, uint64_t src_addr, uint64_t dst_addr)
+				       struct i3c_stm32_dma_stream *dma_stream, uint64_t src_addr,
+				       uint64_t dst_addr)
 {
 	if (dma_stream->dma_dev != NULL) {
 		if (!device_is_ready(dma_stream->dma_dev)) {
@@ -1737,29 +1735,31 @@ static int i3c_stm32_init_dma(const struct device *dev)
 	I3C_TypeDef *i3c = config->i3c;
 
 	/*Configure DMA RX */
-	err  = i3c_stm32_dma_stream_config(dev, &data->dma_rx,
-			LL_I3C_DMA_GetRegAddr(i3c, LL_I3C_DMA_REG_DATA_RECEIVE_BYTE), 0);
+	err = i3c_stm32_dma_stream_config(
+		dev, &data->dma_rx, LL_I3C_DMA_GetRegAddr(i3c, LL_I3C_DMA_REG_DATA_RECEIVE_BYTE),
+		0);
 	if (err != 0) {
 		return err;
 	}
 
 	/*Configure DMA RS */
-	err  = i3c_stm32_dma_stream_config(dev, &data->dma_rs,
-			LL_I3C_DMA_GetRegAddr(i3c, LL_I3C_DMA_REG_STATUS), 0);
+	err = i3c_stm32_dma_stream_config(dev, &data->dma_rs,
+					  LL_I3C_DMA_GetRegAddr(i3c, LL_I3C_DMA_REG_STATUS), 0);
 	if (err != 0) {
 		return err;
 	}
 
 	/*Configure DMA TX */
-	err = i3c_stm32_dma_stream_config(dev, &data->dma_tx, 0,
-			LL_I3C_DMA_GetRegAddr(i3c, LL_I3C_DMA_REG_DATA_TRANSMIT_BYTE));
+	err = i3c_stm32_dma_stream_config(
+		dev, &data->dma_tx, 0,
+		LL_I3C_DMA_GetRegAddr(i3c, LL_I3C_DMA_REG_DATA_TRANSMIT_BYTE));
 	if (err != 0) {
 		return err;
 	}
 
 	/*Configure DMA TC */
 	err = i3c_stm32_dma_stream_config(dev, &data->dma_tc, 0,
-			LL_I3C_DMA_GetRegAddr(i3c, LL_I3C_DMA_REG_CONTROL));
+					  LL_I3C_DMA_GetRegAddr(i3c, LL_I3C_DMA_REG_CONTROL));
 	if (err != 0) {
 		return err;
 	}
@@ -2264,8 +2264,8 @@ int i3c_stm32_ibi_disable(const struct device *dev, struct i3c_device_desc *targ
 #endif /* CONFIG_I3C_USE_IBI */
 
 #ifdef CONFIG_I3C_STM32_DMA
-static void i3c_stm32_tx_rx_msg_config(const struct device *dma_dev,
-		void *user_data, uint32_t channel, int status)
+static void i3c_stm32_tx_rx_msg_config(const struct device *dma_dev, void *user_data,
+				       uint32_t channel, int status)
 {
 	const struct device *dev = (const struct device *)user_data;
 

diff --git a/dts/bindings/i3c/st,stm32-i3c.yaml b/dts/bindings/i3c/st,stm32-i3c.yaml
@@ -9,39 +9,39 @@ compatible: "st,stm32-i3c"
 include: [i3c-controller.yaml, pinctrl-device.yaml]
 
 properties:
-  reg:
-    required: true
-
-  interrupts:
-    required: true
-
-  pinctrl-names:
-    required: true
-
-  dmas:
-    description: |
-      Optional DMA channel specifier, required for DMA transactions.
-      For example dmas for TX/RX/TC/RS on I3C
-         	dmas = <&gpdma1 0 120 STM32_DMA_PERIPH_RX
-          &gpdma1 1 121 STM32_DMA_PERIPH_TX
-          &gpdma1 2 122 (STM32_DMA_PERIPH_TX | STM32_DMA_MEM_32BITS | STM32_DMA_PERIPH_32BITS)
-          &gpdma1 3 123 (STM32_DMA_PERIPH_RX | STM32_DMA_MEM_32BITS | STM32_DMA_PERIPH_32BITS)>;
-
-      With, in each cell of the dmas specifier:
-      - &gpdma1: dma controller phandle
-      - 0: channel number (0 to Max-Channel minus 1). From 0 to 7 on stm32h5x.
-      - 120: slot number (request which could be given by the GPDMA)
-      - STM32_DMA_PERIPH_RX: channel configuration (only for srce/dest data size, priority)
-
-      For example dmas for TX/RX/TC/RS on I3C
-          dmas = <&gpdma1 0 120 STM32_DMA_PERIPH_RX
-          &gpdma1 1 121 STM32_DMA_PERIPH_TX
-          &gpdma1 2 122 (STM32_DMA_PERIPH_TX | STM32_DMA_MEM_32BITS | STM32_DMA_PERIPH_32BITS)
-          &gpdma1 3 123 (STM32_DMA_PERIPH_RX | STM32_DMA_MEM_32BITS | STM32_DMA_PERIPH_32BITS)>;
-
-  dma-names:
-    description: |
-      DMA channel name. If DMA should be used, expected value is "rx" "tx" "tc" "rs".
-
-      For example
-         dma-names = "rx", "tx", "tc", "rs";
+	reg:
+		required: true
+
+	interrupts:
+		required: true
+
+	pinctrl-names:
+		required: true
+
+	dmas:
+		description: |
+			Optional DMA channel specifier, required for DMA transactions.
+			For example dmas for TX/RX/TC/RS on I3C
+					dmas = <&gpdma1 0 120 STM32_DMA_PERIPH_RX
+					&gpdma1 1 121 STM32_DMA_PERIPH_TX
+					&gpdma1 2 122 (STM32_DMA_PERIPH_TX | STM32_DMA_MEM_32BITS | STM32_DMA_PERIPH_32BITS)
+					&gpdma1 3 123 (STM32_DMA_PERIPH_RX | STM32_DMA_MEM_32BITS | STM32_DMA_PERIPH_32BITS)>;
+
+			With, in each cell of the dmas specifier:
+			- &gpdma1: dma controller phandle
+			- 0: channel number (0 to Max-Channel minus 1). From 0 to 7 on stm32h5x.
+			- 120: slot number (request which could be given by the GPDMA)
+			- STM32_DMA_PERIPH_RX: channel configuration (only for srce/dest data size, priority)
+
+			For example dmas for TX/RX/TC/RS on I3C
+					dmas = <&gpdma1 0 120 STM32_DMA_PERIPH_RX
+					&gpdma1 1 121 STM32_DMA_PERIPH_TX
+					&gpdma1 2 122 (STM32_DMA_PERIPH_TX | STM32_DMA_MEM_32BITS | STM32_DMA_PERIPH_32BITS)
+					&gpdma1 3 123 (STM32_DMA_PERIPH_RX | STM32_DMA_MEM_32BITS | STM32_DMA_PERIPH_32BITS)>;
+
+	dma-names:
+		description: |
+			DMA channel name. If DMA should be used, expected value is "rx" "tx" "tc" "rs".
+
+			For example
+				 dma-names = "rx", "tx", "tc", "rs";