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SPI Engine: simplify interconnect #1502

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SPI Engine: simplify interconnect #1502

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ed1483a
SPI Engine Execution: split counters
LBFFilho Aug 15, 2024
3c56531
SPI Engine Execution: split shift register logic
LBFFilho Aug 15, 2024
88ed47a
SPI Engine Execution: pipeline sdo alignment
LBFFilho Aug 15, 2024
831e115
Guidelines fix
LBFFilho Nov 11, 2024
e6937d4
SPI Engine: decouple SDO data handshake from control
LBFFilho Sep 6, 2024
77104fa
SPI Engine: simplify interconnect
LBFFilho Oct 11, 2024
491e2fd
axi_ad5766: add interconnect control
LBFFilho Oct 29, 2024
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21 changes: 18 additions & 3 deletions docs/regmap/adi_regmap_spi_engine.txt
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Original file line number Diff line number Diff line change
Expand Up @@ -9,7 +9,7 @@ ENDTITLE
REG
0x00
VERSION
Version of the peripheral. Follows semantic versioning. Current version 1.03.00.
Version of the peripheral. Follows semantic versioning. Current version 1.04.01.
ENDREG

FIELD
Expand All @@ -19,13 +19,13 @@ RO
ENDFIELD

FIELD
[15:8] 0x00000003
[15:8] 0x00000004
VERSION_MINOR
RO
ENDFIELD

FIELD
[7:0] 0x00000000
[7:0] 0x00000001
VERSION_PATCH
RO
ENDFIELD
Expand Down Expand Up @@ -447,6 +447,21 @@ ENDFIELD
############################################################################################
############################################################################################

REG
0x43
OFFLOAD0_SDO_SRC_SEL
ENDREG

FIELD
[31:0] 0x00000000
OFFLOAD0_SDO_SRC_SEL
RW
Selects data source for SDO offload. 0=SDO memory, 1=SDO stream (DMA).
ENDFIELD

############################################################################################
############################################################################################

REG
0x44
OFFLOAD0_CDM_FIFO
Expand Down
2 changes: 2 additions & 0 deletions library/axi_ad5766/Makefile
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Expand Up @@ -22,6 +22,8 @@ XILINX_DEPS += ../spi_engine/interfaces/spi_engine_ctrl.xml
XILINX_DEPS += ../spi_engine/interfaces/spi_engine_ctrl_rtl.xml
XILINX_DEPS += ../spi_engine/interfaces/spi_engine_offload_ctrl.xml
XILINX_DEPS += ../spi_engine/interfaces/spi_engine_offload_ctrl_rtl.xml
XILINX_DEPS += ../../spi_engine/interfaces/spi_engine_interconnect_ctrl.xml
XILINX_DEPS += ../../spi_engine/interfaces/spi_engine_interconnect_ctrl_rtl.xml

XILINX_LIB_DEPS += util_cdc

Expand Down
11 changes: 9 additions & 2 deletions library/axi_ad5766/axi_ad5766.v
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@@ -1,6 +1,6 @@
// ***************************************************************************
// ***************************************************************************
// Copyright (C) 2017-2023 Analog Devices, Inc. All rights reserved.
// Copyright (C) 2017-2024 Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
Expand Down Expand Up @@ -112,7 +112,11 @@ module axi_ad5766 #(

input ctrl_enable,
output ctrl_enabled,
input ctrl_mem_reset
input ctrl_mem_reset,

// SPI engine interconnect interface

output interconnect_dir
);

// internal wires
Expand Down Expand Up @@ -186,6 +190,8 @@ module axi_ad5766 #(
wire ctrl_is_enabled;
reg spi_enabled = 1'b0;

assign interconnect_dir = spi_enabled;

always @(posedge ctrl_clk) begin
if (ctrl_enable == 1'b1) begin
ctrl_do_enable <= 1'b1;
Expand Down Expand Up @@ -231,6 +237,7 @@ module axi_ad5766 #(
assign spi_enable_s = ctrl_enable;
assign ctrl_enabled = spi_enable_s | spi_active;
assign spi_mem_reset_s = ctrl_mem_reset;
assign interconnect_dir = ctrl_enabled;
end endgenerate

assign spi_cmd_rd_addr_next = spi_cmd_rd_addr + 1;
Expand Down
10 changes: 9 additions & 1 deletion library/axi_ad5766/axi_ad5766_ip.tcl
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@@ -1,5 +1,5 @@
###############################################################################
## Copyright (C) 2017-2023 Analog Devices, Inc. All rights reserved.
## Copyright (C) 2017-2024 Analog Devices, Inc. All rights reserved.
### SPDX short identifier: ADIBSD
###############################################################################

Expand Down Expand Up @@ -62,9 +62,17 @@ adi_add_bus "spi_engine_offload_ctrl" "slave" \
{ "status_sync_data" "sync_data"} \
}

adi_add_bus "m_interconnect_ctrl" "master" \
"analog.com:interface:spi_engine_interconnect_ctrl_rtl:1.0" \
"analog.com:interface:spi_engine_interconnect_ctrl:1.0" \
{ \
{"interconnect_dir" "interconnect_dir"} \
}

adi_add_bus_clock "ctrl_clk" "spi_engine_offload_ctrl"
adi_add_bus_clock "spi_clk" "spi_engine_ctrl" "spi_resetn"
adi_add_bus_clock "dma_clk" "dma_fifo_tx"
adi_add_bus_clock "spi_clk" "m_interconnect_ctrl" "resetn"

adi_add_auto_fpga_spec_params
ipx::create_xgui_files [ipx::current_core]
Expand Down
16 changes: 15 additions & 1 deletion library/spi_engine/axi_spi_engine/axi_spi_engine.v
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Expand Up @@ -123,6 +123,7 @@ module axi_spi_engine #(

output offload0_sdo_wr_en,
output [(DATA_WIDTH-1):0] offload0_sdo_wr_data,
output offload0_sdo_src_sel,

output offload0_mem_reset,
output offload0_enable,
Expand All @@ -133,7 +134,7 @@ module axi_spi_engine #(
input [7:0] offload_sync_data
);

localparam PCORE_VERSION = 'h010300;
localparam PCORE_VERSION = 'h010401;
localparam S_AXI = 0;
localparam UP_FIFO = 1;

Expand Down Expand Up @@ -298,6 +299,7 @@ module axi_spi_engine #(

reg offload0_enable_reg;
reg offload0_mem_reset_reg;
reg offload0_sdo_src_sel_reg;
wire offload0_enabled_s;

// the software reset should reset all the registers
Expand All @@ -306,12 +308,14 @@ module axi_spi_engine #(
up_irq_mask <= 'h00;
offload0_enable_reg <= 1'b0;
offload0_mem_reset_reg <= 1'b0;
offload0_sdo_src_sel_reg <= 1'b0;
end else begin
if (up_wreq_s) begin
case (up_waddr_s)
8'h20: up_irq_mask <= up_wdata_s;
8'h40: offload0_enable_reg <= up_wdata_s[0];
8'h42: offload0_mem_reset_reg <= up_wdata_s[0];
8'h43: offload0_sdo_src_sel_reg <= up_wdata_s[0];
endcase
end
end
Expand Down Expand Up @@ -362,6 +366,7 @@ module axi_spi_engine #(
8'h3c: up_rdata_ff <= sdi_fifo_out_data; /* PEEK register */
8'h40: up_rdata_ff <= {offload0_enable_reg};
8'h41: up_rdata_ff <= {offload0_enabled_s};
8'h43: up_rdata_ff <= {offload0_sdo_src_sel_reg};
8'h80: up_rdata_ff <= CFG_INFO_0;
8'h81: up_rdata_ff <= CFG_INFO_1;
8'h82: up_rdata_ff <= CFG_INFO_2;
Expand Down Expand Up @@ -649,6 +654,15 @@ module axi_spi_engine #(
.out_clk (spi_clk),
.out_bits (offload0_mem_reset));

sync_bits #(
.NUM_OF_BITS (1),
.ASYNC_CLK (ASYNC_SPI_CLK)
) i_offload_sdo_src_sel_sync (
.in_bits (offload0_sdo_src_sel_reg),
.out_resetn (spi_resetn),
.out_clk (spi_clk),
.out_bits (offload0_sdo_src_sel));

sync_bits #(
.NUM_OF_BITS (3),
.ASYNC_CLK (ASYNC_SPI_CLK)
Expand Down
3 changes: 3 additions & 0 deletions library/spi_engine/axi_spi_engine/axi_spi_engine_constr.ttcl
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Expand Up @@ -26,6 +26,9 @@ set_false_path -quiet \
set_false_path -quiet \
-to [get_cells -quiet -hierarchical -filter {NAME =~ *i_offload_enabled_sync/cdc_sync_stage1_reg* && IS_SEQUENTIAL}]

set_false_path -quiet \
-to [get_cells -quiet -hierarchical -filter {NAME =~ *i_offload_sdo_src_sel_sync/cdc_sync_stage1_reg* && IS_SEQUENTIAL}]

set_false_path -quiet \
-to [get_cells -quiet -hierarchical -filter {NAME =~ *i_offload_mem_reset_sync/cdc_sync_stage1_reg* && IS_SEQUENTIAL}]

Expand Down
1 change: 1 addition & 0 deletions library/spi_engine/axi_spi_engine/axi_spi_engine_ip.tcl
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Expand Up @@ -57,6 +57,7 @@ adi_add_bus "spi_engine_offload_ctrl0" "master" \
{ "offload0_cmd_wr_data" "cmd_wr_data"} \
{ "offload0_sdo_wr_en" "sdo_wr_en"} \
{ "offload0_sdo_wr_data" "sdo_wr_data"} \
{ "offload0_sdo_src_sel" "sdo_src_sel"} \
{ "offload0_enable" "enable"} \
{ "offload0_enabled" "enabled"} \
{ "offload0_mem_reset" "mem_reset"} \
Expand Down
2 changes: 2 additions & 0 deletions library/spi_engine/interfaces/Makefile
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Expand Up @@ -18,6 +18,8 @@ XML_FLIST += spi_engine_ctrl.xml
XML_FLIST += spi_engine_ctrl_rtl.xml
XML_FLIST += spi_engine_offload_ctrl.xml
XML_FLIST += spi_engine_offload_ctrl_rtl.xml
XML_FLIST += spi_engine_interconnect_ctrl.xml
XML_FLIST += spi_engine_interconnect_ctrl_rtl.xml

M_FLIST := *.log
M_FLIST += *.jou
Expand Down
6 changes: 6 additions & 0 deletions library/spi_engine/interfaces/interfaces_ip.tcl
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Expand Up @@ -39,9 +39,15 @@ adi_if_ports output 1 cmd_wr_en
adi_if_ports output 16 cmd_wr_data
adi_if_ports output 1 sdo_wr_en
adi_if_ports output -1 sdo_wr_data
adi_if_ports output 1 sdo_src_sel
adi_if_ports output 1 mem_reset
adi_if_ports output 1 enable
adi_if_ports input 1 enabled
adi_if_ports output 1 sync_ready
adi_if_ports input 1 sync_valid
adi_if_ports input 8 sync_data

# Interconnect control interface

adi_if_define "spi_engine_interconnect_ctrl"
adi_if_ports output 1 interconnect_dir
1 change: 1 addition & 0 deletions library/spi_engine/scripts/spi_engine.tcl
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Expand Up @@ -63,6 +63,7 @@ proc spi_engine_create {{name "spi_engine"} {data_width 32} {async_spi_clk 1} {n
ad_ip_parameter $interconnect CONFIG.NUM_OF_SDI $num_sdi

ad_connect $axi_regmap/spi_engine_offload_ctrl0 $offload/spi_engine_offload_ctrl
ad_connect $offload/m_interconnect_ctrl $interconnect/s_interconnect_ctrl
ad_connect $offload/spi_engine_ctrl $interconnect/s0_ctrl
ad_connect $axi_regmap/spi_engine_ctrl $interconnect/s1_ctrl
ad_connect $interconnect/m_ctrl $execution/ctrl
Expand Down
1 change: 1 addition & 0 deletions library/spi_engine/spi_engine_execution/Makefile
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Expand Up @@ -7,6 +7,7 @@
LIBRARY_NAME := spi_engine_execution

GENERIC_DEPS += spi_engine_execution.v
GENERIC_DEPS += spi_engine_execution_shiftreg.v

XILINX_DEPS += spi_engine_execution_constr.ttcl
XILINX_DEPS += spi_engine_execution_ip.tcl
Expand Down
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