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SPI Engine: simplify interconnect #1502
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Commits on Oct 9, 2024
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SPI Engine Execution: split counters
Split up the different counters for better readability. Might synthesize down to slightly larger logic. Signed-off-by: Laez Barbosa <[email protected]>
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Commits on Oct 31, 2024
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SPI Engine Execution: split shift register logic
Moved shift register logic to separate module Signed-off-by: Laez Barbosa <[email protected]>
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Commits on Nov 6, 2024
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SPI Engine Execution: pipeline sdo alignment
Split path between sdo data input and sdo shift register, which includes a barrel shifter. Signed-off-by: Laez Barbosa <[email protected]>
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Commits on Nov 11, 2024
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Commits on Nov 12, 2024
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SPI Engine: decouple SDO data handshake from control
Switched SDO source control to software (memory-mapped register). SDO data can now be clocked in independently from the offload trigger. This allows lower latencies for executing transfers, since the data can be obtained from the DMA before the trigger. It also better separates the command path from the data path Signed-off-by: Laez Barbosa <[email protected]>
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SPI Engine: simplify interconnect
Make the interconnect use an external signal for switching between sources, so it becomes just a collection of muxes, reducing latency. This signal is generated based on the software-controlled offload enable, but is sourced from the offload module to avoid unnecessary CDCs. This commit makes the use of SYNC optional. Signed-off-by: Laez Barbosa <[email protected]>
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axi_ad5766: add interconnect control
Signed-off-by: Laez Barbosa <[email protected]>
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