SPI Engine: simplify interconnect #1502
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Split up the different counters for better readability. Might synthesize down to slightly larger logic. Signed-off-by: Laez Barbosa <[email protected]>
Moved shift register logic to separate module Signed-off-by: Laez Barbosa <[email protected]>
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Split path between sdo data input and sdo shift register, which includes a barrel shifter. Signed-off-by: Laez Barbosa <[email protected]>
Signed-off-by: Laez Barbosa <[email protected]>
Switched SDO source control to software (memory-mapped register). SDO data can now be clocked in independently from the offload trigger. This allows lower latencies for executing transfers, since the data can be obtained from the DMA before the trigger. It also better separates the command path from the data path Signed-off-by: Laez Barbosa <[email protected]>
Make the interconnect use an external signal for switching between sources, so it becomes just a collection of muxes, reducing latency. This signal is generated based on the software-controlled offload enable, but is sourced from the offload module to avoid unnecessary CDCs. This commit makes the use of SYNC optional. Signed-off-by: Laez Barbosa <[email protected]>
Signed-off-by: Laez Barbosa <[email protected]>
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PR Description
Simplifies the interconnect logic, which is now just a set of muxes controlled by a signal from the offload module.
This makes the SYNC instructions optional, and reduces the trigger to first instruction latency.
Since it acts as a substitute for the offload module, axi_ad5766 had to be updated as well in order for it to provide the same interconnect control signal.
(This PR should be merged after #1501)
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