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Issues list

Feature: Generate covergroup for accesses to registers
#34 opened Oct 18, 2024 by quoll99
Backdoor access by better use of configure() or add_hdl_path()
#33 opened Sep 12, 2024 by paul-demo
Feature: option to replace the base class of generated registers
#31 opened Jul 19, 2024 by Furetur
1
generate verilog file, not system verilog.
#30 opened Feb 1, 2024 by yqdvan
2
Clear Namespace DB on subsequent exports.
#28 opened Jan 23, 2024 by hughjackson
[v3.0] During export, check for identifier collisions in output enhancement New feature or request
#26 opened Nov 7, 2023 by amykyta3
[v3.0] Add support for donttest/doncompare
#23 opened Jun 17, 2023 by amykyta3
[v3.0] Refactor to align better with official UVM 1.2 user guide
#21 opened Mar 25, 2023 by amykyta3 v3.0
[v3.0] Add better support for vertical re-use of UVM register models
#20 opened Mar 25, 2023 by amykyta3 v3.0
[v3.0] Add better user control for when virtual registers are used
#19 opened Mar 25, 2023 by amykyta3 v3.0
[v3.0] Add identifier filter
#18 opened Mar 25, 2023 by amykyta3 v3.0
[v3.0] Improve user-extensibility of generated UVM code
#17 opened Mar 25, 2023 by amykyta3 v3.0
[v3.0] hdl_path property does not work with regard to addrmap and regfile components
#13 opened May 14, 2022 by eeeeewwz v3.0
2
ProTip! What’s not been updated in a month: updated:<2024-10-25.