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where test_map_3_inst is a addrmap component instance. The question is, as you can see, I dynamically assign a hdl_path property to test_map_3_inst, but in generated UVM RAL model, the hdl_path is not generated:
It seems like only register components with hdl_path properties results in a add_hdl_path_slice() function call, like this:
Being not familiar with UVM, in my opinion, ultimately all hdl_path in different hierarchies will be concatenated for RTL design verification. Is there some special consideration about the hdl_path property assigned in different components?
The text was updated successfully, but these errors were encountered:
Just wanted to post here that I did not forget about this issue.
I'm planning a significant refactor of the UVM generator (see issues tagged in v3.0 milestone), and plan to address this then.
amykyta3
changed the title
hdl_path property does not work with regard to addrmap and regfile components
[v3.0] hdl_path property does not work with regard to addrmap and regfile components
Mar 25, 2023
Hi,
I write SystemRDL like this:
where
test_map_3_inst
is a addrmap component instance. The question is, as you can see, I dynamically assign a hdl_path property totest_map_3_inst
, but in generated UVM RAL model, the hdl_path is not generated:It seems like only register components with hdl_path properties results in a add_hdl_path_slice() function call, like this:
where
shared_3
is areg
component instance, and generated UVM RAL:Being not familiar with UVM, in my opinion, ultimately all
hdl_path
in different hierarchies will be concatenated for RTL design verification. Is there some special consideration about thehdl_path
property assigned in different components?The text was updated successfully, but these errors were encountered: