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Currently, the UVM exporter does nothing to protect the generated output from using restricted SystemVerilog keywords.
Add a keyword filter, similar to what was done for the regblock generator: https://github.com/SystemRDL/PeakRDL-regblock/blob/main/src/peakrdl_regblock/identifier_filter.py
regblock
The text was updated successfully, but these errors were encountered:
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Currently, the UVM exporter does nothing to protect the generated output from using restricted SystemVerilog keywords.
Add a keyword filter, similar to what was done for the
regblock
generator: https://github.com/SystemRDL/PeakRDL-regblock/blob/main/src/peakrdl_regblock/identifier_filter.pyThe text was updated successfully, but these errors were encountered: