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@riscv-non-isa

RISC-V Non-ISA Specifications

The Open-Standard Instruction Set Architecture
README.md

Welcome to the RISC-V Non-ISA Specifications 👋

RISC-V Logo

Non-ISA specifications do not add new instructions, create or change opcodes, or in any way modify the RISC-V ISA. They do help us to develop an ecosystem around the ISA Specifications.

Things you'll find here include:

  • ABI Documentation
  • Architecture Tests
  • Specifications like Debug, Processor Trace, and Software Interrupts

If you don't find what you're looking for here, try one of our other GitHub organizations:

Popular repositories Loading

  1. riscv-asm-manual riscv-asm-manual Public

    RISC-V Assembly Programmer's Manual

    Makefile 1.4k 238

  2. riscv-elf-psabi-doc riscv-elf-psabi-doc Public

    A RISC-V ELF psABI Document

    Python 714 164

  3. riscv-arch-test riscv-arch-test Public

    Assembly 516 204

  4. riscv-sbi-doc riscv-sbi-doc Public

    Documentation for the RISC-V Supervisor Binary Interface

    Makefile 354 91

  5. rvv-intrinsic-doc rvv-intrinsic-doc Public

    C 297 89

  6. riscv-trace-spec riscv-trace-spec Public

    RISC-V Processor Trace Specification

    C 165 47

Repositories

Showing 10 of 35 repositories
  • riscv-acpi-rimt Public

    RISC-V ACPI I/O Mapping Table Specification

    riscv-non-isa/riscv-acpi-rimt’s past year of commit activity
    Makefile 2 CC-BY-4.0 2 0 1 Updated Nov 22, 2024
  • iopmp-spec Public

    This repository contains the specification source for the RISC-V IOPMP Specification. This document proposes a Physical Memory Protection Unit of Input/Output devices, IOPMP for short, to regulate the accesses issued from the bus masters.

    riscv-non-isa/iopmp-spec’s past year of commit activity
    Makefile 15 CC-BY-4.0 4 4 0 Updated Nov 22, 2024
  • tg-nexus-trace Public

    RISC-V Nexus Trace TG documentation and reference code

    riscv-non-isa/tg-nexus-trace’s past year of commit activity
    C 44 CC-BY-4.0 33 5 0 Updated Nov 22, 2024
  • riscv-c-api-doc Public

    Documentation of the RISC-V C API

    riscv-non-isa/riscv-c-api-doc’s past year of commit activity
    Makefile 75 CC-BY-4.0 41 17 11 Updated Nov 21, 2024
  • riscv-asm-manual Public

    RISC-V Assembly Programmer's Manual

    riscv-non-isa/riscv-asm-manual’s past year of commit activity
    Makefile 1,447 CC-BY-4.0 238 9 9 Updated Nov 21, 2024
  • riscv-elf-psabi-doc Public

    A RISC-V ELF psABI Document

    riscv-non-isa/riscv-elf-psabi-doc’s past year of commit activity
    Python 714 CC-BY-4.0 164 55 26 Updated Nov 21, 2024
  • riscv-ap-tee Public

    This repo holds the work area and revisions of the non-ISA specification created by the RISC-V AP-TEE TG. This specification defines the programming interfaces (ABI) to support the Confidential VM Extension (CoVE) confidential computing architecture for RISC-V application-processor platforms.

    riscv-non-isa/riscv-ap-tee’s past year of commit activity
    Makefile 51 CC-BY-4.0 20 29 1 Updated Nov 20, 2024
  • rvv-intrinsic-doc Public
    riscv-non-isa/rvv-intrinsic-doc’s past year of commit activity
    C 297 BSD-3-Clause 89 20 3 Updated Nov 19, 2024
  • riscv-iommu Public

    RISC-V IOMMU Specification

    riscv-non-isa/riscv-iommu’s past year of commit activity
    C 96 CC-BY-4.0 17 0 2 Updated Nov 19, 2024
  • riscv-brs Public

    The Boot and Runtime Services (BRS) specification provides the software requirements for system vendors and Operating System Vendors (OSVs) to interoperate with one another by providing expectations for the Operating System (OS) to utilize in acts of device discovery, system management, and other rich operations provided in this specification.

    riscv-non-isa/riscv-brs’s past year of commit activity
    TeX 41 CC-BY-4.0 13 15 1 Updated Nov 19, 2024
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