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@riscv-non-isa RISC-V Non-ISA Specifications

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    35 repositories

    • riscv-ap-tee-io

      Public
      This TG will define AP-TEE-IO ABI extensions to provide Confidential VM-assigned devices with secure direct access to confidential memory as well as MMIO, removing the dependence on para-virtualized I/O.
      tee-io
      Makefile
      •
      Creative Commons Attribution 4.0 International
      •4•10•8•1•Updated Nov 26, 2024Nov 26, 2024

    • riscv-security-model

      Public
      RISC-V Security Model
      Makefile
      •
      Creative Commons Attribution 4.0 International
      •14•29•3•0•Updated Nov 25, 2024Nov 25, 2024

    • riscv-trace-spec

      Public
      RISC-V Processor Trace Specification
      C
      •
      Creative Commons Attribution 4.0 International
      •47•165•23•12•Updated Nov 25, 2024Nov 25, 2024

    • iopmp-spec

      Public
      This repository contains the specification source for the RISC-V IOPMP Specification. This document proposes a Physical Memory Protection Unit of Input/Output devices, IOPMP for short, to regulate the accesses issued from the bus masters.
      Makefile
      •
      Creative Commons Attribution 4.0 International
      •4•15•5•0•Updated Nov 25, 2024Nov 25, 2024

    • riscv-external-debug-security

      Public
      The RISC-V External Debug Security Specification
      Makefile
      •
      Creative Commons Attribution 4.0 International
      •2•19•2•1•Updated Nov 25, 2024Nov 25, 2024

    • riscv-acpi-rimt

      Public
      RISC-V ACPI I/O Mapping Table Specification
      Makefile
      •
      Creative Commons Attribution 4.0 International
      •2•2•0•1•Updated Nov 22, 2024Nov 22, 2024

    • tg-nexus-trace

      Public
      RISC-V Nexus Trace TG documentation and reference code
      nexustracerisc-v
      C
      •
      Creative Commons Attribution 4.0 International
      •33•44•5•0•Updated Nov 22, 2024Nov 22, 2024

    • riscv-c-api-doc

      Public
      Documentation of the RISC-V C API
      Makefile
      •
      Creative Commons Attribution 4.0 International
      •41•75•17•11•Updated Nov 21, 2024Nov 21, 2024

    • riscv-asm-manual

      Public
      RISC-V Assembly Programmer's Manual
      Makefile
      •
      Creative Commons Attribution 4.0 International
      •238•1.4k•9•9•Updated Nov 21, 2024Nov 21, 2024

    • riscv-elf-psabi-doc

      Public
      A RISC-V ELF psABI Document
      Python
      •
      Creative Commons Attribution 4.0 International
      •165•715•55•27•Updated Nov 21, 2024Nov 21, 2024

    • riscv-ap-tee

      Public
      This repo holds the work area and revisions of the non-ISA specification created by the RISC-V AP-TEE TG. This specification defines the programming interfaces (ABI) to support the Confidential VM Extension (CoVE) confidential computing architecture for RISC-V application-processor platforms.
      securityvirtualizationteetsmconfidential-computingconfidential-vmh-extensionsmmttsupervisor-domains
      Makefile
      •
      Creative Commons Attribution 4.0 International
      •21•51•29•1•Updated Nov 20, 2024Nov 20, 2024

    • rvv-intrinsic-doc

      Public
      C
      •
      BSD 3-Clause "New" or "Revised" License
      •89•298•20•3•Updated Nov 19, 2024Nov 19, 2024

    • riscv-iommu

      Public
      RISC-V IOMMU Specification
      C
      •
      Creative Commons Attribution 4.0 International
      •17•98•0•2•Updated Nov 19, 2024Nov 19, 2024

    • riscv-brs

      Public
      The Boot and Runtime Services (BRS) specification provides the software requirements for system vendors and Operating System Vendors (OSVs) to interoperate with one another by providing expectations for the Operating System (OS) to utilize in acts of device discovery, system management, and other rich operations provided in this specification.
      platformfirmwarestandardsinteroperabilityuefidevicetreeacpismbiosrisc-vbrs-i
      TeX
      •
      Creative Commons Attribution 4.0 International
      •13•41•15•2•Updated Nov 19, 2024Nov 19, 2024

    • riscv-rqsc

      Public
      Specification Documentation Repository for the RQSC RISC-V Quality of Services Controllers Table definition
      Makefile
      •
      Creative Commons Attribution 4.0 International
      •0•0•0•0•Updated Nov 18, 2024Nov 18, 2024

    • riscv-server-platform

      Public
      The RISC-V Server Platform specification defines a standardized set of hardware and sofware capabilities, that portable system software, such as operating systems and hypervisors, can rely on being present in a RISC-V server platform.
      platformserverosstandardsinteroperabilityuefihypervisorsacpirisc-vbrs-i
      Makefile
      •
      Creative Commons Attribution 4.0 International
      •4•8•8•0•Updated Nov 18, 2024Nov 18, 2024

    • riscv-toolchain-conventions

      Public
      Documenting the expected behaviour and supported command-line switches for GNU and LLVM based RISC-V toolchains
      Makefile
      •
      Creative Commons Attribution 4.0 International
      •35•145•15•7•Updated Nov 15, 2024Nov 15, 2024

    • riscv-arch-test

      Public
      Assembly
      •
      Apache License 2.0
      •204•519•64•40•Updated Nov 13, 2024Nov 13, 2024

    • riscv-rpmi

      Public
      RISC-V Platform Management Interface Specification. OS-agnostic messaging interface for system management and control
      platformmessagingstandardsinteroperabilityriscvrpmiriscv-rpmi
      Makefile
      •
      Creative Commons Attribution 4.0 International
      •8•8•1•0•Updated Nov 11, 2024Nov 11, 2024

    • riscv-sbi-doc

      Public
      Documentation for the RISC-V Supervisor Binary Interface
      Makefile
      •
      Creative Commons Attribution 4.0 International
      •91•354•13•4•Updated Nov 8, 2024Nov 8, 2024

    • riscv-semihosting

      Public
      Makefile
      •
      Creative Commons Attribution Share Alike 4.0 International
      •8•28•1•0•Updated Nov 8, 2024Nov 8, 2024

    • server-soc

      Public
      The repo holds the draft non-ISA Server SoC specification being developed by the Server SoC specification TG and to release intermediate releases of the specification on milestones. Further downstream this repo will be used to release specifications for public review.
      TeX
      •
      Creative Commons Attribution 4.0 International
      •7•20•1•0•Updated Oct 15, 2024Oct 15, 2024

    • riscv-acpi-ffh

      Public
      The repo will be used to hold the draft non-ISA RISC-V ACPI Functional Fixed Hardware (FFH) specification
      Makefile
      •
      Creative Commons Attribution 4.0 International
      •3•3•1•0•Updated Oct 10, 2024Oct 10, 2024

    • riscv-device-tree-doc

      Public
      RISC-V Specific Device Tree Documentation
      Python
      •3•41•1•1•Updated Jul 9, 2024Jul 9, 2024

    • e-trace-encap

      Public
      E-Trace Encapsulation Specification
      Makefile
      •
      Creative Commons Attribution 4.0 International
      •0•3•0•0•Updated Jul 5, 2024Jul 5, 2024

    • riscv-cbqri

      Public
      This repo holds the work area and revisions of a QoS register interface for caches and memory controllers specification. The QoS register interface is a non-ISA specification that supports configuring resource allocations to applications and monitoring the resource usage by applications.
      Makefile
      •
      Creative Commons Attribution 4.0 International
      •7•3•0•1•Updated Jul 2, 2024Jul 2, 2024

    • riscv-ras-eri

      Public
      The (RAS Error-record Register Interface) RERI provides a specification to augment RAS features in RISC-V SOC hardware to standardize reporting and logging of errors by means of a memory-mapped register interface to enable error detection, provide the facility to log the detected errors (including their severity, nature, and location), and confi…
      TeX
      •
      Creative Commons Attribution 4.0 International
      •4•8•0•0•Updated May 24, 2024May 24, 2024

    • riscv-iommu-invalidation

      Public
      IOMMU Address Translation Cache Invalidation Commands Extensions
      Makefile
      •
      Creative Commons Attribution 4.0 International
      •0•0•0•0•Updated May 2, 2024May 2, 2024

    • server-soc-ts

      Public
      Test suite for Server SoC
      Apache License 2.0
      •4•3•0•0•Updated Jan 12, 2024Jan 12, 2024

    • riscv-arch-test-reports

      Public
      HTML
      •6•11•0•2•Updated Dec 27, 2023Dec 27, 2023