Add support for Trace Ingress Port (TIP) on CVA6 V5.1.0 #3971
This workflow is awaiting approval from a maintainer in #2601
Triggered via pull request
November 25, 2024 14:16
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This workflow is awaiting approval from a maintainer in #2601
ci.yml
on: pull_request
build-riscv-tests
Matrix: execute-riscv32-tests
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Matrix: execute-riscv64-tests
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