Add support for Trace Ingress Port (TIP) on CVA6 V5.1.0

[dassheladiya]

Overview

• Adds support for Trace Ingress Port (TIP) on CVA6 V5.1.0

• TIP is Interface between a RISC-V hart and the trace encoder

• It generates information about the instruction retired.

• The implementation is compliant with the Efficient Trace for RISC-V standard Version 2.0.2(https://github.com/riscv-non-isa/riscv-trace-spec/releases/download/v2.0.2/riscv-trace-spec-asciidoc.pdf), specifically:

• Chapter 4.1: Instruction Trace Interface Requirements

• Chapter 4.2: Instruction Trace Interface

• The current implementation supports the following TIP signals: iretire, itype, cause, tval, priv, iaddr, and time. For Instruction Type (itype) encoding, it supports the following: Exception, Interrupt, Exception or interrupt return, Nontaken branch, Taken branch, Uninferable jump.

Changed

• Added new files:
  • core/cva6_tip.sv
  • core/encoder_16_4.sv
• Changes made:
  • core/Flist.cva6 : Added paths.
  • core/cva6.sv : Added TIP and instantiating the cva6_tip block.
  • corev_apu/src/ariane.sv : Added TIP.
  • corev_apu/tb/ariane_testharness.sv : Added TIP for simulation.
• The TIP interface can be enabled or disabled using the IsTIP flag

What I have been able to test so far:

• Simulation: Executed C binaries and observed the waveform of TIP.
• FPGA: A program(in a loop approximately 10 instructions ) was executed on the FPGA, and the output was observed on the Integrated Logic Analyzer (ILA).

What I have not yet tested:

• Did not perform any formal verification.

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[JeanRochCoulon]

Hello @dassheladiya Thanks for this nice feature.
First of all, I encourage you to sign-up the Eclipse ECA to be eligible to contribute to OpenHW Group.
In the meantime, the CONTRIBUTING.md contains information to ease the contribution. One is the command to fix the Verible format.

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[JeanRochCoulon]

@dassheladiya For reminder, your PR need to be rebase to allow the merge.

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