Cherry-pick to earlgrey_1.0.0: [spi_host,flash] Add additional PMOD Flash tests for the BoB

hw/top_earlgrey/data/ip/chip_spi_host_testplan.hjson

@@ -32,7 +32,7 @@
       tests: ["chip_sw_spi_host_tx_rx"]
       bazel: [
         "//sw/device/tests:spi_host_winbond_flash_test",
-        "//sw/device/tests/pmod:spi_host_macronix_flash_test"
+        "//sw/device/tests/pmod:spi_host_macronix1Gb_flash_test"
       ]
     }
     {

sw/device/tests/pmod/BUILD

@@ -17,8 +17,8 @@ load("@bazel_skylib//lib:dicts.bzl", "dicts")
 package(default_visibility = ["//visibility:public"])
 
 opentitan_test(
-    name = "spi_host_macronix_flash_test",
-    srcs = ["spi_host_macronix_flash_test.c"],
+    name = "spi_host_macronix1Gb_flash_test",
+    srcs = ["spi_host_macronix1Gb_flash_test.c"],
     exec_env = dicts.add(
         EARLGREY_TEST_ENVS,
         EARLGREY_SILICON_OWNER_ROM_EXT_ENVS,
@@ -55,6 +55,36 @@ opentitan_test(
     ],
 )
 
+opentitan_test(
+    name = "spi_host_macronix128Mb_flash_test",
+    srcs = ["spi_host_macronix128Mb_flash_test.c"],
+    exec_env = {
+        "//hw/top_earlgrey:fpga_cw310_rom_with_fake_keys": None,
+        "//hw/top_earlgrey:fpga_cw310_test_rom": None,
+    },
+    fpga = fpga_params(
+        tags = [
+            "manual",
+            "pmod",
+        ],  # Requires the PMOD::BoB.
+    ),
+    deps = [
+        "//hw/top_earlgrey/sw/autogen:top_earlgrey",
+        "//sw/device/lib/arch:device",
+        "//sw/device/lib/base:memory",
+        "//sw/device/lib/base:mmio",
+        "//sw/device/lib/dif:spi_host",
+        "//sw/device/lib/runtime:hart",
+        "//sw/device/lib/runtime:log",
+        "//sw/device/lib/runtime:print",
+        "//sw/device/lib/testing:spi_device_testutils",
+        "//sw/device/lib/testing:spi_flash_testutils",
+        "//sw/device/lib/testing:spi_host_testutils",
+        "//sw/device/lib/testing/test_framework:ottf_main",
+        "//sw/device/tests:spi_host_flash_test_impl",
+    ],
+)
+
 opentitan_test(
     name = "spi_host_gigadevice256Mb_flash_test",
     srcs = ["spi_host_gigadevice256Mb_flash_test.c"],
@@ -117,6 +147,37 @@ opentitan_test(
     ],
 )
 
+opentitan_test(
+    name = "spi_host_issi256Mb_flash_test",
+    srcs = ["spi_host_issi256Mb_flash_test.c"],
+    exec_env = {
+        "//hw/top_earlgrey:fpga_cw310_rom_with_fake_keys": None,
+        "//hw/top_earlgrey:fpga_cw310_test_rom": None,
+    },
+    fpga = fpga_params(
+        tags = [
+            "manual",
+            "pmod",
+        ],  # Requires the PMOD::BoB.
+    ),
+    deps = [
+        "//hw/top_earlgrey/sw/autogen:top_earlgrey",
+        "//sw/device/lib/arch:device",
+        "//sw/device/lib/base:memory",
+        "//sw/device/lib/base:mmio",
+        "//sw/device/lib/dif:pinmux",
+        "//sw/device/lib/dif:spi_host",
+        "//sw/device/lib/runtime:hart",
+        "//sw/device/lib/runtime:log",
+        "//sw/device/lib/runtime:print",
+        "//sw/device/lib/testing:spi_device_testutils",
+        "//sw/device/lib/testing:spi_flash_testutils",
+        "//sw/device/lib/testing:spi_host_testutils",
+        "//sw/device/lib/testing/test_framework:ottf_main",
+        "//sw/device/tests:spi_host_flash_test_impl",
+    ],
+)
+
 opentitan_test(
     name = "spi_host_micron512Mb_flash_test",
     srcs = ["spi_host_micron512Mb_flash_test.c"],
@@ -148,6 +209,37 @@ opentitan_test(
     ],
 )
 
+opentitan_test(
+    name = "spi_host_winbond1Gb_flash_test",
+    srcs = ["spi_host_winbond1Gb_flash_test.c"],
+    exec_env = {
+        "//hw/top_earlgrey:fpga_cw310_rom_with_fake_keys": None,
+        "//hw/top_earlgrey:fpga_cw310_test_rom": None,
+    },
+    fpga = fpga_params(
+        tags = [
+            "manual",
+            "pmod",
+        ],  # Requires the PMOD::BoB.
+    ),
+    deps = [
+        "//hw/top_earlgrey/sw/autogen:top_earlgrey",
+        "//sw/device/lib/arch:device",
+        "//sw/device/lib/base:memory",
+        "//sw/device/lib/base:mmio",
+        "//sw/device/lib/dif:pinmux",
+        "//sw/device/lib/dif:spi_host",
+        "//sw/device/lib/runtime:hart",
+        "//sw/device/lib/runtime:log",
+        "//sw/device/lib/runtime:print",
+        "//sw/device/lib/testing:spi_device_testutils",
+        "//sw/device/lib/testing:spi_flash_testutils",
+        "//sw/device/lib/testing:spi_host_testutils",
+        "//sw/device/lib/testing/test_framework:ottf_main",
+        "//sw/device/tests:spi_host_flash_test_impl",
+    ],
+)
+
 opentitan_test(
     name = "i2c_host_accelerometer_test",
     srcs = ["i2c_host_accelerometer_test.c"],

sw/device/tests/pmod/spi_host_gigadevice1Gb_flash_test.c

@@ -80,15 +80,15 @@ bool test_main(void) {
    * the Quad SPI.
    */
   enum GigadeviceVendorSpecific {
-    kManufactureId = 0xC8,
+    kManufacturerId = 0xC8,
     kPageQuadProgramOpcode = 0xC2,
   };
 
   status_t result = OK_STATUS();
   EXECUTE_TEST(result, test_software_reset, &spi_host);
   EXECUTE_TEST(result, test_read_sfdp, &spi_host);
   EXECUTE_TEST(result, test_sector_erase, &spi_host);
-  EXECUTE_TEST(result, test_read_jedec, &spi_host, kManufactureId);
+  EXECUTE_TEST(result, test_read_jedec, &spi_host, kManufacturerId);
   EXECUTE_TEST(result, test_page_program, &spi_host);
   if (is_4_bytes_address_mode_supported()) {
     EXECUTE_TEST(result, test_4bytes_address, &spi_host);

sw/device/tests/pmod/spi_host_gigadevice256Mb_flash_test.c

@@ -26,7 +26,7 @@ static_assert(__BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__,
 
 OTTF_DEFINE_TEST_CONFIG();
 
-static void init_test(dif_spi_host_t *spi_host) {
+static void init_test(dif_spi_host_t *spi_host, dif_pinmux_index_t csb_pin) {
   dif_pinmux_t pinmux;
   mmio_region_t base_addr =
       mmio_region_from_addr(TOP_EARLGREY_PINMUX_AON_BASE_ADDR);
@@ -47,7 +47,6 @@ static void init_test(dif_spi_host_t *spi_host) {
       CHECK(false, "Device not supported %u", kDeviceType);
       break;
   }
-  dif_pinmux_index_t csb_pin = kTopEarlgreyPinmuxMioOutIoc11;
   CHECK_STATUS_OK(
       spi_host1_pinmux_connect_to_bob(&pinmux, csb_pin, platform_id));
 
@@ -68,33 +67,44 @@ static void init_test(dif_spi_host_t *spi_host) {
 }
 
 bool test_main(void) {
-  dif_spi_host_t spi_host;
-
-  init_test(&spi_host);
   enum GigadeviceVendorSpecific {
-    kManufactureId = 0xC8,
+    kManufacturerId = 0xC8,
     kPageQuadProgramOpcode = 0x32,
   };
 
+  // Chip select pins for the different 256Mb GigaDevice SPI Flashes available
+  // via PMOD
+  dif_pinmux_index_t csb_pins[] = {
+      kTopEarlgreyPinmuxMioOutIoc11,
+      kTopEarlgreyPinmuxMioOutIoa6,
+  };
+
   status_t result = OK_STATUS();
-  EXECUTE_TEST(result, test_software_reset, &spi_host);
-  EXECUTE_TEST(result, test_read_sfdp, &spi_host);
-  EXECUTE_TEST(result, test_sector_erase, &spi_host);
-  EXECUTE_TEST(result, test_read_jedec, &spi_host, kManufactureId);
-  EXECUTE_TEST(result, test_enable_quad_mode, &spi_host);
-  EXECUTE_TEST(result, test_page_program, &spi_host);
-  if (is_4_bytes_address_mode_supported()) {
-    EXECUTE_TEST(result, test_4bytes_address, &spi_host);
+  for (size_t i = 0; i < ARRAYSIZE(csb_pins); ++i) {
+    LOG_INFO("Testing flash device %u", (uint32_t)(i + 1));
+    dif_spi_host_t spi_host;
+
+    init_test(&spi_host, csb_pins[i]);
+
+    EXECUTE_TEST(result, test_software_reset, &spi_host);
+    EXECUTE_TEST(result, test_read_sfdp, &spi_host);
+    EXECUTE_TEST(result, test_sector_erase, &spi_host);
+    EXECUTE_TEST(result, test_read_jedec, &spi_host, kManufacturerId);
+    EXECUTE_TEST(result, test_enable_quad_mode, &spi_host);
+    EXECUTE_TEST(result, test_page_program, &spi_host);
+    if (is_4_bytes_address_mode_supported()) {
+      EXECUTE_TEST(result, test_4bytes_address, &spi_host);
+    }
+    EXECUTE_TEST(result, test_fast_read, &spi_host);
+    EXECUTE_TEST(result, test_dual_read, &spi_host);
+    EXECUTE_TEST(result, test_quad_read, &spi_host);
+
+    // The Gigadevice flash `4PP` opcode operates in 1-1-4 mode.
+    EXECUTE_TEST(result, test_page_program_quad, &spi_host,
+                 kPageQuadProgramOpcode, kTransactionWidthMode114);
+    EXECUTE_TEST(result, test_erase_32k_block, &spi_host);
+    EXECUTE_TEST(result, test_erase_64k_block, &spi_host);
   }
-  EXECUTE_TEST(result, test_fast_read, &spi_host);
-  EXECUTE_TEST(result, test_dual_read, &spi_host);
-  EXECUTE_TEST(result, test_quad_read, &spi_host);
-
-  // The Gigadevice flash `4PP` opcode operates in 1-1-4 mode.
-  EXECUTE_TEST(result, test_page_program_quad, &spi_host,
-               kPageQuadProgramOpcode, kTransactionWidthMode114);
-  EXECUTE_TEST(result, test_erase_32k_block, &spi_host);
-  EXECUTE_TEST(result, test_erase_64k_block, &spi_host);
 
   return status_ok(result);
 }

sw/device/tests/pmod/spi_host_issi256Mb_flash_test.c

@@ -0,0 +1,102 @@
+// Copyright lowRISC contributors (OpenTitan project).
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+#include <assert.h>
+
+#include "sw/device/lib/arch/device.h"
+#include "sw/device/lib/base/macros.h"
+#include "sw/device/lib/base/memory.h"
+#include "sw/device/lib/base/mmio.h"
+#include "sw/device/lib/dif/dif_pinmux.h"
+#include "sw/device/lib/dif/dif_spi_host.h"
+#include "sw/device/lib/runtime/hart.h"
+#include "sw/device/lib/runtime/log.h"
+#include "sw/device/lib/runtime/print.h"
+#include "sw/device/lib/testing/spi_device_testutils.h"
+#include "sw/device/lib/testing/spi_flash_testutils.h"
+#include "sw/device/lib/testing/spi_host_testutils.h"
+#include "sw/device/lib/testing/test_framework/check.h"
+#include "sw/device/lib/testing/test_framework/ottf_main.h"
+#include "sw/device/tests/spi_host_flash_test_impl.h"
+
+#include "hw/top_earlgrey/sw/autogen/top_earlgrey.h"
+
+static_assert(__BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__,
+              "This test assumes the target platform is little endian.");
+
+OTTF_DEFINE_TEST_CONFIG();
+
+static void init_test(dif_spi_host_t *spi_host) {
+  dif_pinmux_t pinmux;
+  mmio_region_t base_addr =
+      mmio_region_from_addr(TOP_EARLGREY_PINMUX_AON_BASE_ADDR);
+  CHECK_DIF_OK(dif_pinmux_init(base_addr, &pinmux));
+
+  spi_pinmux_platform_id_t platform_id = kSpiPinmuxPlatformIdCount;
+  switch (kDeviceType) {
+    case kDeviceSilicon:
+      platform_id = kSpiPinmuxPlatformIdTeacup;
+      break;
+    case kDeviceFpgaCw310:
+      platform_id = kSpiPinmuxPlatformIdCw310;
+      break;
+    case kDeviceFpgaCw340:
+      platform_id = kSpiPinmuxPlatformIdCw340;
+      break;
+    default:
+      CHECK(false, "Device not supported: %u", kDeviceType);
+      break;
+  }
+  dif_pinmux_index_t csb_pin = kTopEarlgreyPinmuxMioOutIoc12;
+  CHECK_STATUS_OK(
+      spi_host1_pinmux_connect_to_bob(&pinmux, csb_pin, platform_id));
+
+  base_addr = mmio_region_from_addr(TOP_EARLGREY_SPI_HOST1_BASE_ADDR);
+  CHECK_DIF_OK(dif_spi_host_init(base_addr, spi_host));
+
+  CHECK(kClockFreqUsbHz <= UINT32_MAX, "kClockFreqUsbHz must fit in uint32_t");
+
+  CHECK_DIF_OK(dif_spi_host_configure(
+                   spi_host,
+                   (dif_spi_host_config_t){
+                       .spi_clock = 1000000,
+                       .peripheral_clock_freq_hz = (uint32_t)kClockFreqUsbHz,
+                   }),
+               "SPI_HOST config failed!");
+
+  CHECK_DIF_OK(dif_spi_host_output_set_enabled(spi_host, true));
+}
+
+bool test_main(void) {
+  dif_spi_host_t spi_host;
+
+  init_test(&spi_host);
+
+  enum IssiVendorSpecific {
+    kManufacturerId = 0x9D,
+    // The ISSI flash `4PP` opcode operates using 4-byte addresses.
+    // Instead, we use the `PPQ` Quad Input Page Program operation.
+    kPageQuadProgramOpcode = 0x32,
+  };
+
+  status_t result = OK_STATUS();
+  EXECUTE_TEST(result, test_software_reset, &spi_host);
+  EXECUTE_TEST(result, test_read_sfdp, &spi_host);
+  EXECUTE_TEST(result, test_sector_erase, &spi_host);
+  EXECUTE_TEST(result, test_read_jedec, &spi_host, kManufacturerId);
+  EXECUTE_TEST(result, test_enable_quad_mode, &spi_host);
+  EXECUTE_TEST(result, test_page_program, &spi_host);
+  if (is_4_bytes_address_mode_supported()) {
+    EXECUTE_TEST(result, test_4bytes_address, &spi_host);
+  }
+  EXECUTE_TEST(result, test_fast_read, &spi_host);
+  EXECUTE_TEST(result, test_dual_read, &spi_host);
+  EXECUTE_TEST(result, test_quad_read, &spi_host);
+  // The ISSI flash `PPQ` opcode operates in 1-1-4 mode.
+  EXECUTE_TEST(result, test_page_program_quad, &spi_host,
+               kPageQuadProgramOpcode, kTransactionWidthMode114);
+  EXECUTE_TEST(result, test_erase_32k_block, &spi_host);
+  EXECUTE_TEST(result, test_erase_64k_block, &spi_host);
+
+  return status_ok(result);
+}