Backport 25065 from master to earlgrey_1.0.0

hw/top_earlgrey/data/chip_testplan.hjson

@@ -22,12 +22,12 @@
     "sw/device/lib/crypto/data/crypto_testplan.hjson"
 
     // IP block specific top level test plans.
-    "hw/top_earlgrey/data/ip/chip_aes_testplan.hjson",
     "hw/top_earlgrey/data/ip/chip_adc_ctrl_testplan.hjson",
+    "hw/top_earlgrey/data/ip/chip_aes_testplan.hjson",
+    "hw/top_earlgrey/data/ip/chip_alert_handler_testplan.hjson",
     "hw/top_earlgrey/data/ip/chip_aon_timer_testplan.hjson",
     "hw/top_earlgrey/data/ip/chip_clkmgr_testplan.hjson",
     "hw/top_earlgrey/data/ip/chip_csrng_testplan.hjson",
-    "hw/top_earlgrey/data/ip/chip_sysrst_ctrl_testplan.hjson",
     "hw/top_earlgrey/data/ip/chip_edn_testplan.hjson",
     "hw/top_earlgrey/data/ip/chip_entropy_src_testplan.hjson",
     "hw/top_earlgrey/data/ip/chip_flash_ctrl_testplan.hjson",
@@ -37,21 +37,21 @@
     "hw/top_earlgrey/data/ip/chip_keymgr_testplan.hjson",
     "hw/top_earlgrey/data/ip/chip_kmac_testplan.hjson",
     "hw/top_earlgrey/data/ip/chip_lc_ctrl_testplan.hjson",
+    "hw/top_earlgrey/data/ip/chip_otbn_testplan.hjson",
     "hw/top_earlgrey/data/ip/chip_otp_ctrl_testplan.hjson",
     "hw/top_earlgrey/data/ip/chip_pwrmgr_testplan.hjson",
     "hw/top_earlgrey/data/ip/chip_rom_ctrl_testplan.hjson",
     "hw/top_earlgrey/data/ip/chip_rstmgr_testplan.hjson",
+    "hw/top_earlgrey/data/ip/chip_rv_core_ibex_testplan.hjson",
+    "hw/top_earlgrey/data/ip/chip_rv_dm_testplan.hjson"
     "hw/top_earlgrey/data/ip/chip_rv_plic_testplan.hjson",
     "hw/top_earlgrey/data/ip/chip_rv_timer_testplan.hjson",
     "hw/top_earlgrey/data/ip/chip_spi_device_testplan.hjson",
     "hw/top_earlgrey/data/ip/chip_spi_host_testplan.hjson",
     "hw/top_earlgrey/data/ip/chip_sram_ctrl_testplan.hjson",
+    "hw/top_earlgrey/data/ip/chip_sysrst_ctrl_testplan.hjson",
     "hw/top_earlgrey/data/ip/chip_uart_testplan.hjson",
     "hw/top_earlgrey/data/ip/chip_usbdev_testplan.hjson",
-    "hw/top_earlgrey/data/ip/chip_alert_handler_testplan.hjson",
-    "hw/top_earlgrey/data/ip/chip_rv_dm_testplan.hjson"
-    "hw/top_earlgrey/data/ip/chip_rv_core_ibex_testplan.hjson",
-    "hw/top_earlgrey/data/ip/chip_otbn_testplan.hjson",
   ]
 
   testpoints: [

hw/top_earlgrey/data/ip/chip_aes_testplan.hjson

@@ -266,7 +266,7 @@
       bazel: [
         "//sw/device/tests/crypto:aes_sideload_functest",
         "//sw/device/tests/crypto:aes_kwp_sideload_functest",
-        "//sw/device/tests/crypto:keymgr_sideload_aes_test",
+        "//sw/device/tests:keymgr_sideload_aes_test",
       ]
     }
     {

hw/top_earlgrey/data/ip/chip_hmac_testplan.hjson

@@ -109,7 +109,6 @@
       lc_states: ["PROD"]
       tests: []
       bazel: [
-        "//sw/device/tests/crypto/cryptotest:hash_kat",
         "//sw/device/tests/crypto:hmac_sha256_functest",
       ]
     }

hw/top_earlgrey/data/ip/chip_pwrmgr_testplan.hjson

@@ -79,10 +79,9 @@
             `wakeup_en` CSR, bring the chip to normal sleep, optionally disabling the source's
             clock, have the source issue a wakeup event and verify `wake_info` indicates the
             expected wakeup.
-            SiVal: No need to run this, run chip_sw_pwrmgr_random_sleep_all_wake_ups instead.
             '''
       stage: V2
-      si_stage: NA
+      si_stage: SV3
       tests: ["chip_sw_pwrmgr_normal_sleep_all_wake_ups"]
       bazel: ["//sw/device/tests:pwrmgr_normal_sleep_all_wake_ups"]
     }
@@ -135,10 +134,9 @@
             This verifies ALL wake up sources. This also verifies that the pwrmgr sequencing is
             working correctly as expected. X-ref'ed with all individual IP tests. Similar to
             chip_pwrmgr_sleep_all_wake_ups, except `control.main_pd_n` is set to 0.
-            SiVal: No need to run this, run chip_sw_pwrmgr_random_sleep_all_wake_ups instead.
             '''
       stage: V2
-      si_stage: NA
+      si_stage: SV3
       tests: ["chip_sw_pwrmgr_deep_sleep_all_wake_ups"]
       bazel: ["//sw/device/tests:pwrmgr_deep_sleep_all_wake_ups"]
     }
@@ -160,7 +158,7 @@
             No need to run this, run chip_sw_pwrmgr_random_sleep_all_reset_reqs instead.
             '''
       stage: V2
-      si_stage: NA
+      si_stage: SV3
       features: [
         "PWRMGR.LOW_POWER.ENTRY",
         "PWRMGR.LOW_POWER.DISABLE_POWER"

hw/top_earlgrey/data/ip/chip_spi_device_testplan.hjson

@@ -99,7 +99,7 @@
                 - Clears the busy bit to allow the upstream SPI host to proceed to the next command.
             '''
       stage: V2
-      si_stage: SV3
+      si_stage: NA
       lc_states: [ "PROD" ]
       features: [
         "SPI_DEVICE.MODE.PASSTHROUGH",
@@ -161,7 +161,7 @@
                which is why the "features" list is empty. It may be reclassifed in the future.
              '''
       stage: V3
-      si_stage: None
+      si_stage: SV3
       lc_states: [ "PROD" ]
       features: ["SPI_DEVICE.CFG",
                  "SPI_DEVICE.JEDEC_CC",

hw/top_earlgrey/data/ip/chip_usbdev_testplan.hjson

@@ -110,7 +110,7 @@
       si_stage: SV3
       lc_states: ["PROD"]
       tests: []
-      bazel: ["//sw/device/tests:usbdev_sof_test"]
+      bazel: []
     }
     {
       name: chip_sw_usbdev_setup_rx
@@ -339,7 +339,7 @@
       si_stage: SV3
       lc_states: ["PROD"]
       tests: []
-      bazel: ["//sw/device/tests:usbdev_suspend_resume_test"]
+      bazel: []
     }
     {
       name: chip_sw_usbdev_aon_wake_reset
@@ -422,7 +422,7 @@
       si_stage: SV3
       lc_states: ["PROD"]
       tests: []
-      bazel: ["//sw/device/tests:usbdev_toggle_restore_test"]
+      bazel: []
     }
   ]
 }