Backport 25065 from master to earlgrey_1.0.0

[engdoreis]

Update testplans and SiVal test suites

This Backport depends on #25091 to be merged first.

[matutem]

I flagged some issues with clkmgr and pwrmgr tests, and filed an issue for the clkmgr testpoints mentioned. Also, we need to resolve if redundant tests in pwrmgr are really worth running and taking CI time.

Obviously these issues need to be resolved in master, and if some change is made they should be cherry-picked.

[engdoreis]

Thanks @matutem for the review.
Do we never want to run these tests that you commented on in Silicon?
If yes, I should change the PR and keep them as NA, otherwise we merge it as it is, and then we open issues to adjust the tests as you suggested.

[matutem]

@engdoreis I will be working on #25177 now and expect to have "//sw/device/tests:clkmgr_jitter_frequency_test" ready and testing jitter frequency more thoroughly. I will change "//sw/device/tests:clkmgr_jitter_test" to be a test of jitter_regwen. Incidentally, the various DV tests in chip_sw_clkmgr_jitter enable jitter, but they are obviously not SiVal tests.

As for the other changes, my concern about pwrmgr is weak, since it may be useful to have simpler tests than the more comprehensive one and the tests are quick, so they are good to go.

I am concerned about the chip_sw_flash_init testpoint: I think we need a more robust test in master before cherry picking it.

So we need a new issue to address the shortcomings of chip_sw_flash_init in master before cherry picking it.

Bottom line, all but the clkmgr and flash_ctrl testplan changes are okay. WDYT? @moidx?

[engdoreis]

@matutem I made the suggested changes.

[matutem]

Thanks Douglas. LGTM