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add module #107

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@@ -0,0 +1,9 @@

module hello(input clk);

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⚠️ [verible-verilog-lint] reported by reviewdog 🐶
Declared module does not match the first dot-delimited component of file name: "module" [Style: file-names] [module-filename]


initial
begin: proc_he
$display("helllo");

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⚠️ [verible-verilog-lint] reported by reviewdog 🐶
Use spaces, not tabs. [Style: tabs] [no-tabs]

@@ -0,0 +1,10 @@

module hello(input clk);

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⚠️ [verible-verilog-lint] reported by reviewdog 🐶
Declared module does not match the first dot-delimited component of file name: "module" [Style: file-names] [module-filename]

initial

begin: proc_he
$display("helllo");

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⚠️ [verible-verilog-lint] reported by reviewdog 🐶
Use spaces, not tabs. [Style: tabs] [no-tabs]


always
begin: proc_clk
#(20) $display("tic");
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⚠️ [verible-verilog-lint] reported by reviewdog 🐶
Use spaces, not tabs. [Style: tabs] [no-tabs]

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