Add support for adaq776x-1 series and add missing features

Documentation/devicetree/bindings/iio/adc/adi,ad7768-1.yaml

@@ -4,18 +4,26 @@
 $id: http://devicetree.org/schemas/iio/adc/adi,ad7768-1.yaml#
 $schema: http://devicetree.org/meta-schemas/core.yaml#
 
-title: Analog Devices AD7768-1 ADC device driver
+title: Analog Devices AD7768-1 ADC family device driver
 
 maintainers:
   - Michael Hennerich <[email protected]>
 
 description: |
-  Datasheet at:
-    https://www.analog.com/media/en/technical-documentation/data-sheets/ad7768-1.pdf
+  Analog Devices AD7768-1 24-Bit Single Channel Low Power sigma-delta ADC family
+
+  https://www.analog.com/media/en/technical-documentation/data-sheets/ad7768-1.pdf
+  https://www.analog.com/media/en/technical-documentation/data-sheets/adaq7767-1.pdf
+  https://www.analog.com/media/en/technical-documentation/data-sheets/adaq7768-1.pdf
+  https://www.analog.com/media/en/technical-documentation/data-sheets/adaq7769-1.pdf
 
 properties:
   compatible:
-    const: adi,ad7768-1
+    enum:
+      - adi,ad7768-1
+      - adi,adaq7767-1
+      - adi,adaq7768-1
+      - adi,adaq7769-1
 
   reg:
     maxItems: 1
@@ -39,6 +47,23 @@ properties:
     description:
       ADC reference voltage supply
 
+  adi,aaf-gain:
+    description: |
+      Specifies the gain of the Analog Anti-Aliasing Filter (AAF) applied to the
+      ADC input, measured in milli-units. The AAF provides additional signal
+      rejection within the frequency range of fs ± f3dB, where fs is the sampling
+      frequency, and f3dB is the -3dB cutoff frequency. The specific values of
+      fs and f3dB, as well as the rejection intensity, depend on the digital
+      filter configuration.
+
+      This parameter is required for the ADAQ7767-1 and ADAQ7769-1 devices.
+      The gain is determined by the selected input pin:
+      * For the ADAQ7767-1: The input selection of IN1±, IN2± or IN3±.
+      * For the ADAQ7769-1: The connections of OUT_PGA to IN1_AAF+, IN2_AAF+,
+        or IN3_AAF+.
+    $ref: /schemas/types.yaml#/definitions/uint16
+    enum: [143, 364, 1000]
+
   adi,sync-in-gpios:
     maxItems: 1
     description:
@@ -47,6 +72,14 @@ properties:
       in any way, for example if the filter decimation rate changes.
       As the line is active low, it should be marked GPIO_ACTIVE_LOW.
 
+  adi,sync-in-spi:
+    description:
+      Enables synchronization of multiple devices over SPI. This property is
+      used when a signal synchronous to the base MCLK signal cannot be provided
+      via GPIO. It requires the SYNC_OUT pin to be connected to the SYNC_IN pin
+      on the ADC. In the case of multiple devices, the SYNC_OUT pin of one device
+      should be routed to the SYNC_IN pins of the other devices.
+
   reset-gpios:
     maxItems: 1
 
@@ -65,7 +98,6 @@ required:
   - vref-supply
   - spi-cpol
   - spi-cpha
-  - adi,sync-in-gpios
 
 patternProperties:
   "^channel@([0-9]|1[0-5])$":
@@ -89,6 +121,33 @@ patternProperties:
 allOf:
   - $ref: /schemas/spi/spi-peripheral-props.yaml#
 
+  # AAF Gain property only applies to ADAQ7767-1 and ADAQ7769-1 devices
+  - if:
+      properties:
+        compatible:
+          not:
+            contains:
+              enum:
+                - adi,adaq7767-1
+                - adi,adaq7769-1
+    then:
+      properties:
+        adi,aaf-gain: false
+
+  # adi,sync-in-gpios and adi,sync-in-spi are mutually exclusive (neither is also valid)
+  - if:
+      required:
+        - adi,sync-in-gpios
+    then:
+      properties:
+        adi,sync-in-spi: false
+  - if:
+      required:
+        - adi,sync-in-spi
+    then:
+      properties:
+        adi,sync-in-gpios: false
+
 unevaluatedProperties: false
 
 examples:

arch/arm/boot/dts/zynq-zed-adv7511-ad7768-1-evb.dts

@@ -52,7 +52,7 @@
 	};
 
 	axi_spi_engine_0: spi@0x44a00000 {
-		compatible = "adi,axi-spi-engine-1.00.a";
+		compatible = "adi-ex,axi-spi-engine-1.00.a";
 		reg = <0x44a00000 0x1000>;
 		interrupt-parent = <&intc>;
 		interrupts = <0 56 IRQ_TYPE_LEVEL_HIGH>;

arch/arm/boot/dts/zynq-zed-adv7511-adaq7767-1-evb.dts

@@ -0,0 +1,103 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Analog Devices ADAQ7767-1
+ * https://wiki.analog.com/resources/eval/user-guides/ad7768-1
+ *
+ * hdl_project: <ad77681evb/zed>
+ * board_revision: <B>
+ *
+ * Copyright (C) 2024 Analog Devices Inc.
+ */
+/dts-v1/;
+
+#include "zynq-zed.dtsi"
+#include "zynq-zed-adv7511.dtsi"
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+	vref: regulator-vref {
+		compatible = "regulator-fixed";
+		regulator-name = "fixed-supply";
+		regulator-min-microvolt = <4096000>;
+		regulator-max-microvolt = <4096000>;
+		regulator-always-on;
+	};
+
+	clocks {
+		ad7768_1_mclk: clock@0 {
+			#clock-cells = <0>;
+			compatible = "fixed-clock";
+			clock-frequency = <16384000>;
+		};
+	};
+};
+
+&fpga_axi {
+	rx_dma: rx-dmac@0x44a30000 {
+		compatible = "adi,axi-dmac-1.00.a";
+		reg = <0x44a30000 0x1000>;
+		#dma-cells = <1>;
+		interrupt-parent = <&intc>;
+		interrupts = <0 57 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&clkc 16>;
+
+		adi,channels {
+			#size-cells = <0>;
+			#address-cells = <1>;
+
+			dma-channel@0 {
+				reg = <0>;
+				adi,source-bus-width = <32>;
+				adi,source-bus-type = <1>;
+				adi,destination-bus-width = <64>;
+				adi,destination-bus-type = <0>;
+			};
+		};
+	};
+
+	spi_clock: spieng-axi-clkgen@44a70000 {
+		compatible = "adi,axi-clkgen-2.00.a";
+		reg = <0x44a70000 0x10000>;
+		#clock-cells = <0>;
+		clocks = <&clkc 15>, <&clkc 16>;
+		clock-names = "s_axi_aclk", "clkin1";
+	};
+
+	axi_spi_engine_0: spi@0x44a00000 {
+		compatible = "adi-ex,axi-spi-engine-1.00.a";
+		reg = <0x44a00000 0x1000>;
+		interrupt-parent = <&intc>;
+		interrupts = <0 56 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&clkc 15 &spi_clock>;
+		clock-names = "s_axi_aclk", "spi_clk";
+		num-cs = <1>;
+
+		#address-cells = <0x1>;
+		#size-cells = <0x0>;
+
+		adaq7767_1: adc@0 {
+			compatible = "adi,adaq7767-1";
+			reg = <0>;
+			spi-max-frequency = <40000000>;
+			spi-cpol;
+			spi-cpha;
+			vref-supply = <&vref>;
+			adi,sync-in-spi;
+			adi,aaf-gain = <143>;
+			reset-gpios = <&gpio0 86 GPIO_ACTIVE_LOW>;
+			clocks = <&ad7768_1_mclk>;
+			clock-names = "mclk";
+			dmas = <&rx_dma 0>;
+			dma-names = "rx";
+			#io-channel-cells = <1>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			channel@0 {
+				reg = <0>;
+				label = "channel_0";
+			};
+		};
+	};
+};

arch/arm/boot/dts/zynq-zed-adv7511-adaq7768-1-evb.dts

@@ -0,0 +1,102 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Analog Devices ADAQ7768-1
+ * https://wiki.analog.com/resources/eval/user-guides/ad7768-1
+ *
+ * hdl_project: <ad77681evb/zed>
+ * board_revision: <B>
+ *
+ * Copyright (C) 2024 Analog Devices Inc.
+ */
+/dts-v1/;
+
+#include "zynq-zed.dtsi"
+#include "zynq-zed-adv7511.dtsi"
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+	vref: regulator-vref {
+		compatible = "regulator-fixed";
+		regulator-name = "fixed-supply";
+		regulator-min-microvolt = <4096000>;
+		regulator-max-microvolt = <4096000>;
+		regulator-always-on;
+	};
+
+	clocks {
+		ad7768_1_mclk: clock@0 {
+			#clock-cells = <0>;
+			compatible = "fixed-clock";
+			clock-frequency = <16384000>;
+		};
+	};
+};
+
+&fpga_axi {
+	rx_dma: rx-dmac@0x44a30000 {
+		compatible = "adi,axi-dmac-1.00.a";
+		reg = <0x44a30000 0x1000>;
+		#dma-cells = <1>;
+		interrupt-parent = <&intc>;
+		interrupts = <0 57 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&clkc 16>;
+
+		adi,channels {
+			#size-cells = <0>;
+			#address-cells = <1>;
+
+			dma-channel@0 {
+				reg = <0>;
+				adi,source-bus-width = <32>;
+				adi,source-bus-type = <1>;
+				adi,destination-bus-width = <64>;
+				adi,destination-bus-type = <0>;
+			};
+		};
+	};
+
+	spi_clock: spieng-axi-clkgen@44a70000 {
+		compatible = "adi,axi-clkgen-2.00.a";
+		reg = <0x44a70000 0x10000>;
+		#clock-cells = <0>;
+		clocks = <&clkc 15>, <&clkc 16>;
+		clock-names = "s_axi_aclk", "clkin1";
+	};
+
+	axi_spi_engine_0: spi@0x44a00000 {
+		compatible = "adi-ex,axi-spi-engine-1.00.a";
+		reg = <0x44a00000 0x1000>;
+		interrupt-parent = <&intc>;
+		interrupts = <0 56 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&clkc 15 &spi_clock>;
+		clock-names = "s_axi_aclk", "spi_clk";
+		num-cs = <1>;
+
+		#address-cells = <0x1>;
+		#size-cells = <0x0>;
+
+		adaq7768_1: adc@0 {
+			compatible = "adi,adaq7768-1";
+			reg = <0>;
+			spi-max-frequency = <40000000>;
+			spi-cpol;
+			spi-cpha;
+			vref-supply = <&vref>;
+			adi,sync-in-spi;
+			reset-gpios = <&gpio0 86 GPIO_ACTIVE_LOW>;
+			clocks = <&ad7768_1_mclk>;
+			clock-names = "mclk";
+			dmas = <&rx_dma 0>;
+			dma-names = "rx";
+			#io-channel-cells = <1>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			channel@0 {
+				reg = <0>;
+				label = "channel_0";
+			};
+		};
+	};
+};