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Add support for adaq776x-1 series and add missing features #2587
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Commits on Nov 27, 2024
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dt-bindings: iio: adc: ad7768-1: add new supported parts
Add compatibles for supported parts in the ad7768-1 family: ADAQ7767-1, ADAQ7768-1 and ADAQ7769-1 Add property and checks for AFF gain, supported by ADAQ7767-1 and ADAQ7769-1 parts: adi,aaf-gain Signed-off-by: Jonathan Santos <[email protected]>
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dt-bindings: iio: adc: ad7768-1: add synchronization over SPI property
Add adi,sync-in-spi property to enable synchronization over SPI. This should be used in the case when the GPIO cannot provide a pulse synchronous with the base MCLK signal. User can choose between SPI, GPIO synchronization or neither of them, but only if a external pulse can be provided, for example, by another device in a multidevice setup. Signed-off-by: Jonathan Santos <[email protected]>
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arm: dts: zynq-zed-adv7511-ad7768-1-evb: add support for new spi-engine
Use compatible for new spi-engine implementation. Signed-off-by: Jonathan Santos <[email protected]>
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arm: dts: Add device tree for ADAQ7767-1 on ZedBoard
Enables using the ADAQ7767-1 device on ZedBoard with FMC connector. Signed-off-by: Jonathan Santos <[email protected]>
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arm: dts: Add device tree for ADAQ7768-1 on ZedBoard
Enables using the ADAQ7768-1 device on ZedBoard with FMC connector. Signed-off-by: Jonathan Santos <[email protected]>
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arm: dts: Add device tree for ADAQ7769-1 on ZedBoard
Enables using the ADAQ7769-1 device on ZedBoard with FMC connector. Signed-off-by: Jonathan Santos <[email protected]>
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iio: adc: ad7768-1: set MOSI idle state to high
All supported parts require that the MOSI line stays high while in idle. Configure SPI controller to set MOSI idle state to high. Fixes: 8a15c73 ("iio: adc: Add AD7768-1 ADC basic support") Signed-off-by: Jonathan Santos <[email protected]>
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iio: adc: ad7768-1: add support for Synchronization over SPI
The synchronization method using GPIO requires the generated pulse to be truly synchronous with the base MCLK signal. When it is not possible to do that in hardware, the datasheet recommends using synchronization over SPI, where the generated pulse is already synchronous with MCLK. This requires the SYNC_OUT pin to be connected to SYNC_IN pin. Add the option to handle device synchronization over SPI. Signed-off-by: Jonathan Santos <[email protected]>
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iio: adc: ad7768-1: add filter mode and decimation rate attributes
Separate filter mode and decimation rate from the sampling frequency attribute. The new filter mode attribute enables SINC3 and WIDEBAND filters, which were previously unavailable. Previously, combining decimation and MCLK divider in the sampling frequency obscured performance trade-offs. Lower MCLK divider settings increase power usage, while lower decimation rates reduce precision by decreasing averaging. By creating a decimation attribute, users gain finer control over performance. The addition of those attributes allows a wider range of sampling frequencies and more access to the device features. Co-developed-by: PopPaul2021 <[email protected]> Signed-off-by: PopPaul2021 <[email protected]> Signed-off-by: Jonathan Santos <[email protected]>
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iio: adc: ad7768-1: add multiple scan types to support 16-bits mode
When the device is configured to Sinc5 filter and decimation x8, output data is reduced to 16-bits in order to support 1 MHz of sampling frequency due to clock limitation. Use multiple scan types feature to enable the driver to switch scan type in runtime, making possible to support both 24-bit and 16-bit resolution. Signed-off-by: Jonathan Santos <[email protected]>
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iio: adc: ad7768-1: remove tx_buf from IIO buffer read transfer
The address byte is not needed in the SPI transfer if continuous read mode is enabled. In this case, data readback occurs on the application of SCLK. Remove tx_buf from IIO buffer read transfer to reduce the duration of each transfer and enable the sample rate of 1.024 MHz at 16-bit resolution, given the maximum supported SCLK rate of 20 MHz: - With address byte: (16-bit data + 8-bit address) * 1.024 MHz > 20 MHZ. Insufficient SCLK cycles to drive out the output. - Without address byte: (16-bit data) * 1.024 MHz < 20 MHz. Signed-off-by: Jonathan Santos <[email protected]>
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iio: adc: ad7768-1: use new spi-engine implementation
Add support for new spi-engine implementation on ad7768-1 driver, optimizing offload transfers by reducing CS delay and minimizing the number of commands in the offload FIFO. Without the otimization, there's not enough time between the end of a transfer and the start of the next one, reducing the actual sample rate. Adjust 'tx_data' buffer handling in SPI register read and write functions to ensure endianness consistency with the new spi-engine. Signed-off-by: Jonathan Santos <[email protected]>
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iio: adc: ad7768-1: introduce chip info for future multidevice support
Add Chip info struct in SPI device to store channel information for each supported part. Signed-off-by: Jonathan Santos <[email protected]>
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iio: adc: ad7768-1: use devm_regulator_get_enable_read_voltage
Use devm_regulator_get_enable_read_voltage function as a standard and concise way of reading the voltage from the regulator and keep the regulator enabled. Replace the regulator descriptor with the direct voltage value in the device struct. Signed-off-by: Jonathan Santos <[email protected]>
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iio: adc: ad7768-1: add support for ADAQ776x-1 ADC Family
Add support for ADAQ7767/68/69-1 series, which includes PGIA and Anti-aliasing filter (AAF) gains. The PGA gain is configured in run-time through the scale attribute, if supported by the device. The scale options are updated according to the output data width. The AAF gain is configured in the devicetree and it should correspond to the AAF channel selected in hardware. Signed-off-by: Jonathan Santos <[email protected]>
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