Upgrades to support Vitis AI 1.4 and KV260 (#69)

* Upgrades to support Vitis AI 1.4 and KV260

* updated license identifier

LICENSE

@@ -1,4 +1,4 @@
-Copyright (c) 2020, Xilinx
+Copyright (c) 2021, Xilinx
 All rights reserved.
 
 
@@ -204,3 +204,186 @@ All rights reserved.
    See the License for the specific language governing permissions and
    limitations under the License.
 
+Components: target_factory 1.4.0
+
+
+# Copyright 2019 Xilinx Inc.
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#     http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+
+
+Copyright 2019 Xilinx Inc
+
+
+Components: vart 1.4.0
+
+
+/* Copyright 2019 Xilinx Inc. 
+** 
+** Licensed under the Apache License, Version 2.0 (the "License"); 
+** you may not use this file except in compliance with the License. 
+** You may obtain a copy of the License at 
+** 
+**     http://www.apache.org/licenses/LICENSE-2.0 
+** 
+** Unless required by applicable law or agreed to in writing, software 
+** distributed under the License is distributed on an "AS IS" BASIS, 
+** WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 
+** See the License for the specific language governing permissions and 
+** limitations under the License. 
+*/ 
+
+
+"""
+MIT License
+
+Copyright (c) 2016 Gabriel Stanovsky
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in all
+copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+SOFTWARE.
+"""
+
+
+Copyright 2016, 2019-2021 Xilinx Inc
+Copyright 2016 Gabriel Stanovsky
+Copyright 2018 The TensorFlow Authors
+Copyright statement to Your modifications and
+Copyright (C) Xilinx .Ltd 2019
+
+
+Components: unilog 1.4.0
+
+
+/*
+ * Copyright 2019 Xilinx Inc.
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+
+Copyright 2019 Xilinx Inc
+
+
+Components: xir 1.4.0
+
+
+/*
+ * Copyright 2019 Xilinx Inc.
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+
+Copyright 2019 Xilinx Inc
+
+
+Components: jarro2783-cxxopts
+
+
+/*
+
+Copyright (c) 2014, 2015, 2016, 2017 Jarryd Beck
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in
+all copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+THE SOFTWARE.
+
+*/
+
+
+Copyright (c) 2014 2015 2016 2017 Jarryd Beck 
+
+
+Components: 
+pynqdpu.dpu.kv260.1.4.0.bit
+pynqdpu.dpu.kv260.1.4.0.xclbin
+pynqdpu.dpu.ultra96.1.4.0.bit
+pynqdpu.dpu.ultra96.1.4.0.xclbin
+pynqdpu.dpu.zcu104.1.4.0.bit
+pynqdpu.dpu.zcu104.1.4.0.xclbin
+
+
+Copyright © 2021 Xilinx, Inc.
+
+Redistribution and use in binary form only, without modification, 
+is permitted provided that the following conditions are met:
+
+1. Redistributions must reproduce the above copyright notice, 
+   this list of conditions, the below disclaimer, and the below 
+   third-party copyright notice and license in the documentation 
+   and/or other materials provided with the distribution.
+
+2. The name of Xilinx, Inc. may not be used to endorse or promote 
+   products redistributed with this software without specific 
+   prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY XILINX, INC. "AS IS" AND ANY EXPRESS 
+OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 
+ARE DISCLAIMED. IN NO EVENT SHALL XILINX, INC. BE LIABLE FOR ANY 
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 
+DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE 
+GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
+INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 
+WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE 
+OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, 
+EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

README.md

@@ -10,33 +10,24 @@ In this repository, we currently support the following boards:
 
 * Ultra96
 * ZCU104
-* ZCU111
+* KV260 
 
 Other Zynq Ultrascale+ boards may be supported with few adjustments.
-This repository supports Vitis AI 1.3.2.
+This repository supports Vitis AI 1.4.0.
 
 ## Quick Start
 
-### 1. Upgrading the PYNQ v2.6 image
+### 1. Install
 
-This upgrade step is to make sure users have a DPU-ready image. 
-This step is only required for one time.
+**For the KV260 only:** If you are running DPU-PYNQ on the KV260 you will first need to uninstall 
+the previous version of vitis-ai-runtime. The setup script will install
+VART 1.4.0 automatically.
 
-On your board, run `su` to use super user. Then run the following commands:
-
-```shell
-git clone https://github.com/Xilinx/DPU-PYNQ.git
-cd DPU-PYNQ/upgrade
-make
+```
+apt remove --purge vitis-ai-runtime
 ```
 
-The upgrade process may take up to 1 hour, since a few packages will 
-need to be installed. Please be patient. For more information, users can check
-the [PYNQ v2.6 upgrade instructions](./upgrade/README.md)
-
-### 2. Install
-
-Run the following on board:
+To install the pynq-dpu on your board, simply run:
 
 ```shell
 pip3 install pynq-dpu
@@ -52,14 +43,14 @@ pynq get-notebooks pynq-dpu -p .
 This will make sure the desired notebooks shows up in your jupyter notebook 
 folder.
 
-### 3. Run
+### 2. Run
 
 You are ready to go! Now in jupyter, you can explore the notebooks 
 in `pynq-dpu` folder.
 
 ## Rebuild DPU Block Design
 
-The DPU IP comes from the [Vitis Ai Github](https://github.com/Xilinx/Vitis-AI/tree/v1.3.2).
+The DPU IP comes from the [Vitis Ai Github](https://github.com/Xilinx/Vitis-AI/tree/v1.4.0).
 If you want to rebuild the hardware project, you can refer to the
 [instructions for DPU Hardware Design](./boards/README.md).
 
@@ -73,10 +64,12 @@ These are the overlay files that can be used by the `pynq_dpu` package.
 
 ## Rebuild DPU Models
 
-[DPU models for ZCU104](https://github.com/Xilinx/Vitis-AI/tree/v1.3.2) 
-are available on the Vitis AI GitHub repository.
+[DPU models](https://github.com/Xilinx/Vitis-AI/tree/v1.4) 
+are available on the Vitis AI GitHub repository [model zoo](https://github.com/Xilinx/Vitis-AI/tree/v1.4/models/AI-Model-Zoo),
+where you can find a model-list containing quantized models, as well as pre-compiled .xmodel files
+that can be directly loaded into your DPU application.
 
-If you want to rebuild the DPU models, you can refer to the
+If you want to recompile the DPU models or train your own network, you can refer to the
 [instructions for DPU models](./host/README.md).
 
 
@@ -85,4 +78,4 @@ If you want to rebuild the DPU models, you can refer to the
 
 Copyright (C) 2021 Xilinx, Inc
 
-SPDX-License-Identifier: Apache-2.0 License
+SPDX-License-Identifier: Apache-2.0

boards/ZCU111/dpu_conf.vh → boards/KV260/dpu_conf.vh

@@ -32,11 +32,11 @@
 // | for zcu102 : `define URAM_DISABLE                 
 // |------------------------------------------------------|
 
-`define URAM_DISABLE 
+`define URAM_ENABLE 
 
 //config URAM
 `ifdef URAM_ENABLE
-    `define def_UBANK_IMG_N          5
+    `define def_UBANK_IMG_N          5 
     `define def_UBANK_WGT_N          17
     `define def_UBANK_BIAS           1
 `elsif URAM_DISABLE

boards/KV260/prj_config

@@ -0,0 +1,31 @@
+[clock]
+
+freqHz=300000000:DPUCZDX8G_1.aclk
+freqHz=600000000:DPUCZDX8G_1.ap_clk_2
+
+#id=0:DPUCZDX8G_1.aclk
+#id=1:DPUCZDX8G_1.ap_clk_2
+
+[connectivity]
+
+sp=DPUCZDX8G_1.M_AXI_GP0:HP1
+sp=DPUCZDX8G_1.M_AXI_HP0:HP1
+sp=DPUCZDX8G_1.M_AXI_HP2:HPC1
+
+[advanced]
+misc=:solution_name=link
+param=compiler.addOutputTypes=hw_export
+#param=compiler.addOutputTypes=sd_card
+#param=compiler.skipTimingCheckAndFrequencyScaling=1
+
+[vivado]
+prop=run.impl_1.strategy=Performance_Explore
+#prop=run.impl_1.strategy=Performance_NetDelay_high
+#prop=run.impl_1.strategy=Performance_WLBlockPlacementFanoutOpt
+#prop=run.impl_1.strategy=Performance_WLBlockPlacement
+#prop=run.impl_1.strategy=Performance_ExploreWithRemap
+#prop=run.impl_1.strategy=Performance_BalanceSLRs
+#prop=run.impl_1.strategy=Performance_EarlyBlockPlacement
+#prop=run.impl_1.strategy=Performance_ExtraTimingOpt
+#prop=run.impl_1.strategy=Performance_NetDelay_low
+#param=place.runPartPlacer=0

boards/Makefile

@@ -1,5 +1,5 @@
 BOARD := Ultra96
-SUPPORTED = Ultra96 ZCU104 ZCU111
+SUPPORTED = Ultra96 ZCU104 KV260
 
 # VITIS_PLATFORM can be:
 # 1. built from scratch for specific boards
@@ -10,10 +10,11 @@ endif
 ifeq ($(BOARD),ZCU104)
 VITIS_PLATFORM := $(shell pwd)/$(BOARD)/dpu/dpu.xpfm
 endif
-ifeq ($(BOARD),ZCU111)
+ifeq ($(BOARD),KV260)
 VITIS_PLATFORM := $(shell pwd)/$(BOARD)/dpu/dpu.xpfm
 endif
 
+
 GARBAGE_PATTERNS := *.log *.jou sample_link.ini
 GARBAGE_PATTERNS += binary_container_1 packaged_* tmp_*
 GARBAGE_PATTERNS += scripts kernel_xml .Xil
@@ -26,12 +27,7 @@ RM = rm -f
 RMDIR = rm -rf
 VIVADO := ${VIVADO_ROOT}/bin/vivado
 TARGET := hw
-
-ifeq ($(BOARD),ZCU111)
-KERNEL := DPU_SM
-else
 KERNEL := DPU
-endif
 
 .PHONY: all clean check_env
 all : check_env dpu.xclbin
@@ -57,6 +53,7 @@ DPU_HDLSRCS=\
 	${DIR_PRJ}/kernel_xml/dpu/kernel.xml\
 	${DIR_PRJ}/scripts/package_dpu_kernel.tcl\
 	${DIR_PRJ}/scripts/gen_dpu_xo.tcl\
+	${DIR_PRJ}/scripts/bip_proc.tcl\
 	${DIR_PRJ}/dpu_conf.vh\
 	${DIR_TRD}/dpu_ip/Vitis/dpu/hdl/DPUCZDX8G.v\
 	${DIR_TRD}/dpu_ip/Vitis/dpu/inc/arch_def.vh\
@@ -86,6 +83,8 @@ ${DIR_PRJ}/scripts/gen_dpu_xo.tcl: $(DIR_PRJ)/scripts
 	cp -f ${DIR_TRD}/prj/Vitis/scripts/gen_dpu_xo.tcl $@
 ${DIR_PRJ}/scripts/gen_sfm_xo.tcl: $(DIR_PRJ)/scripts
 	cp -f ${DIR_TRD}/prj/Vitis/scripts/gen_sfm_xo.tcl $@
+${DIR_PRJ}/scripts/bip_proc.tcl : $(DIR_PRJ)/scripts
+	cp -f ${DIR_TRD}/prj/Vitis/scripts/bip_proc.tcl $@
 ${DIR_PRJ}/scripts/package_dpu_kernel.tcl: $(DIR_PRJ)/scripts
 	cp -f ${DIR_TRD}/prj/Vitis/scripts/package_dpu_kernel.tcl $@
 	sed -i 's/set path_to_hdl "..\/..\/dpu_ip"/set path_to_hdl "..\/..\/vitis-ai-git\/dsa\/DPU-TRD\/dpu_ip"/' $@
@@ -136,5 +135,4 @@ clean:
 cleanall: clean
 	$(RMDIR) Ultra96/dpu
 	$(RMDIR) ZCU104/zcu104_dpu
-	$(RMDIR) ZCU111/dpu
 	$(RMDIR) PYNQ-derivative-overlays