VAI 1.3.2 update (#49)

README.md

@@ -13,7 +13,7 @@ In this repository, we currently support the following boards:
 * ZCU111
 
 Other Zynq Ultrascale+ boards may be supported with few adjustments.
-This repository supports Vitis AI 1.3.
+This repository supports Vitis AI 1.3.2.
 
 ## Quick Start
 
@@ -59,7 +59,7 @@ in `pynq-dpu` folder.
 
 ## Rebuild DPU Block Design
 
-The DPU IP comes from the [Vitis Ai Github](https://github.com/Xilinx/Vitis-AI/tree/v1.2.1).
+The DPU IP comes from the [Vitis Ai Github](https://github.com/Xilinx/Vitis-AI/tree/v1.3.2).
 If you want to rebuild the hardware project, you can refer to the
 [instructions for DPU Hardware Design](./boards/README.md).
 
@@ -73,12 +73,16 @@ These are the overlay files that can be used by the `pynq_dpu` package.
 
 ## Rebuild DPU Models
 
-[DPU models for ZCU104](https://github.com/Xilinx/Vitis-AI/tree/v1.3) 
+[DPU models for ZCU104](https://github.com/Xilinx/Vitis-AI/tree/v1.3.2) 
 are available on the Vitis AI GitHub repository.
 
 If you want to rebuild the DPU models, you can refer to the
 [instructions for DPU models](./host/README.md).
 
+
+----
+----
+
 Copyright (C) 2021 Xilinx, Inc
 
-SPDX-License-Identifier: Apache-2.0 License
+SPDX-License-Identifier: Apache-2.0 License

boards/README.md

@@ -85,8 +85,11 @@ board folder. The adjustable settings of the DPU IP include:
 * `DEVICE Configuration`
 
 For more information regarding the DPU IP, you can refer to the [official Vitis
-AI DPU guide](https://github.com/Xilinx/Vitis-AI/blob/master/DPU-TRD/prj/Vitis/README.md).
+AI DPU guide](https://www.xilinx.com/html_docs/vitis_ai/1_3/fke1606771875742.html).
+
+----
+----
 
 Copyright (C) 2021 Xilinx, Inc
 
-SPDX-License-Identifier: Apache-2.0 License
+SPDX-License-Identifier: Apache-2.0 License

host/compile.sh

@@ -7,7 +7,7 @@ if [ "$#" -eq 2 ]; then
 	MODEL_NAME=$2
 else
 	echo "Error: please provide BOARD and MODEL_NAME as arguments."
-	echo "Example: ./compile.sh Ultra96 cf_resnet50_imagenet_224_224_7.7G_1.1"
+	echo "Example: ./compile.sh Ultra96 cf_resnet50_imagenet_224_224_7.7G_1.3"
 	exit 1
 fi
 
@@ -41,8 +41,9 @@ if [ $BOARD = "Ultra96" ]; then
 fi
 
 # ZCU111 and ZCU102 use equivalent DPU configurations
-if [ $BOARD = "ZCU111" ]; then
-	BOARD=ZCU102
+if [ $BOARD = "ZCU111" ] && [ ! -e /opt/vitis_ai/compiler/arch/DPUCZDX8G/ZCU111 ]; then
+	sudo cp -r /opt/vitis_ai/compiler/arch/DPUCZDX8G/ZCU102 \
+		/opt/vitis_ai/compiler/arch/DPUCZDX8G/ZCU111 
 fi
 
 mkdir -p ${BOARD}_${FRAMEWORK}_${MODEL}_build
@@ -78,4 +79,4 @@ fi
 
 rm -f ${MODEL_NAME}*zip
 rm -rf ${MODEL_NAME}
-cd ..
+cd ..

pynq_dpu/__init__.py

@@ -16,7 +16,6 @@
 from .dpu import DpuOverlay
 
 
-__author__ = "Yun Rock Qu, Jingwei Zhang"
 __copyright__ = "Copyright 2021, Xilinx"
 __email__ = "[email protected]"
-__version__ = '1.3.0'
+__version__ = '1.3.2'

pynq_dpu/edge/notebooks/dpu_mnist_classifier.xmodel.link

@@ -1,14 +1,14 @@
 {
 	"Ultra96": {
-        "url": "https://www.xilinx.com/bin/public/openDownload?filename=pynqdpu.dpu_mnist_classifier.ultra96.1.3.0.xmodel",
-        "md5sum": "c2196e3ede6254d56af420efb398182a"
+        "url": "https://www.xilinx.com/bin/public/openDownload?filename=pynqdpu.dpu_mnist_classifier.ultra96.1.3.2.xmodel",
+        "md5sum": "6e2afe0689e4e8b4b59032415369c5ce"
     },
 	"ZCU104": {
-        "url": "https://www.xilinx.com/bin/public/openDownload?filename=pynqdpu.dpu_mnist_classifier.zcu104.1.3.0.xmodel",
-        "md5sum": "a930600fbcdc9c76d1022702e5c04ae9"
+        "url": "https://www.xilinx.com/bin/public/openDownload?filename=pynqdpu.dpu_mnist_classifier.zcu104.1.3.2.xmodel",
+        "md5sum": "ebe11340048df091eaa011bf886e66fe"
     },
 	"ZCU111": {
-        "url": "https://www.xilinx.com/bin/public/openDownload?filename=pynqdpu.dpu_mnist_classifier.zcu111.1.3.0.xmodel",
-        "md5sum": "1c74c6a61c14b0aae825d30ee0179dd4"
+        "url": "https://www.xilinx.com/bin/public/openDownload?filename=pynqdpu.dpu_mnist_classifier.zcu111.1.3.2.xmodel",
+        "md5sum": "50db365992fba4cbf19f7b9d19e33435"
     }
-}
+}

pynq_dpu/edge/notebooks/dpu_resnet50.xmodel.link

@@ -1,14 +1,14 @@
 {
 	"Ultra96": {
-        "url": "https://www.xilinx.com/bin/public/openDownload?filename=pynqdpu.dpu_resnet50.ultra96.1.3.0.xmodel",
-        "md5sum": "489ed4dc13e755d82e3a4cf87bf6866e"
+        "url": "https://www.xilinx.com/bin/public/openDownload?filename=pynqdpu.dpu_resnet50.ultra96.1.3.2.xmodel",
+        "md5sum": "0937f196876ac3ef01d9a6bb8f01ef88"
     },
 	"ZCU104": {
-        "url": "https://www.xilinx.com/bin/public/openDownload?filename=pynqdpu.dpu_resnet50.zcu104.1.3.0.xmodel",
-        "md5sum": "97486654ca4382094abe2b6335c68c99"
+        "url": "https://www.xilinx.com/bin/public/openDownload?filename=pynqdpu.dpu_resnet50.zcu104.1.3.2.xmodel",
+        "md5sum": "79da60ea02bf94383929901c304f0b29"
     },
 	"ZCU111": {
-        "url": "https://www.xilinx.com/bin/public/openDownload?filename=pynqdpu.dpu_resnet50.zcu111.1.3.0.xmodel",
-        "md5sum": "26de9e09930c969ac7ebac0d7277a25b"
+        "url": "https://www.xilinx.com/bin/public/openDownload?filename=pynqdpu.dpu_resnet50.zcu111.1.3.2.xmodel",
+        "md5sum": "7be0eda709e93089f543ca159c2a3eeb"
     }
-}
+}

pynq_dpu/edge/notebooks/dpu_tf_inceptionv1.xmodel.link

@@ -1,14 +1,14 @@
 {
 	"Ultra96": {
-        "url": "https://www.xilinx.com/bin/public/openDownload?filename=pynqdpu.dpu_tf_inceptionv1.ultra96.1.3.0.xmodel",
-        "md5sum": "46c0dee687b4a62f434d082ebc854588"
+        "url": "https://www.xilinx.com/bin/public/openDownload?filename=pynqdpu.dpu_tf_inceptionv1.ultra96.1.3.2.xmodel",
+        "md5sum": "7eaaa490d4c99a2aa2ade4208c96aca3"
     },
 	"ZCU104": {
-        "url": "https://www.xilinx.com/bin/public/openDownload?filename=pynqdpu.dpu_tf_inceptionv1.zcu104.1.3.0.xmodel",
-        "md5sum": "1567bf29acfaea77a58c2f3ca24f9ee3"
+        "url": "https://www.xilinx.com/bin/public/openDownload?filename=pynqdpu.dpu_tf_inceptionv1.zcu104.1.3.2.xmodel",
+        "md5sum": "50f0856cce621881e92f56ecf00111f1"
     },
 	"ZCU111": {
-        "url": "https://www.xilinx.com/bin/public/openDownload?filename=pynqdpu.dpu_tf_inceptionv1.zcu111.1.3.0.xmodel",
-        "md5sum": "9b385f453596d53f82085e02f4dbce08"
+        "url": "https://www.xilinx.com/bin/public/openDownload?filename=pynqdpu.dpu_tf_inceptionv1.zcu111.1.3.2.xmodel",
+        "md5sum": "cd4f2b9b9078de6292c54a977592f9a5"
     }
-}
+}

setup.py

@@ -12,7 +12,6 @@
 #  See the License for the specific language governing permissions and
 #  limitations under the License.
 
-__author__ = "Yun Rock Qu, Jingwei Zhang"
 __copyright__ = "Copyright 2021, Xilinx"
 __email__ = "[email protected]"
 
@@ -104,10 +103,10 @@ def get_board():
 
 def install_vart_pkg(pkg_path, edge):
     os.system('cd {0} && '
-              'wget -O vitis-ai-runtime-1.3.0.pynq.tar.gz '
+              'wget -O vitis-ai-runtime-1.3.2.pynq.tar.gz '
               '"https://www.xilinx.com/bin/public/openDownload?filename='
-              'vitis-ai-runtime-1.3.0.pynq.tar.gz" && '
-              'tar -xvf vitis-ai-runtime-1.3.0.pynq.tar.gz && '
+              'vitis-ai-runtime-1.3.2.pynq.tar.gz" && '
+              'tar -xvf vitis-ai-runtime-1.3.2.pynq.tar.gz && '
               'cd {1} && '
               'apt-get install ./*.deb && '
               'cd ../ && '