feat: update project tt_um_bomba1 from arizaga1/Latin_bomba

Commit: 62d773d6f0c1fd22684e322ba0ab0db1bfea99cb
Workflow: https://github.com/arizaga1/Latin_bomba/actions/runs/8749553597

projects/tt_um_bomba1/LICENSE

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projects/tt_um_bomba1/commit_id.json

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+{
+  "app": "Tiny Tapeout tt06 c74b14ac",
+  "repo": "https://github.com/arizaga1/Latin_bomba",
+  "commit": "62d773d6f0c1fd22684e322ba0ab0db1bfea99cb",
+  "workflow_url": "https://github.com/arizaga1/Latin_bomba/actions/runs/8749553597",
+  "sort_id": 1713530314638,
+  "openlane_version": "OpenLane eaba5192c45aa333ab45216ce1773d75d539e9b3",
+  "pdk_version": "open_pdks cd1748bb197f9b7af62a54507de6624e30363943"
+}

projects/tt_um_bomba1/docs/info.md

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+<!---
+
+This file is used to generate your project datasheet. Please fill in the information below and delete any unused
+sections.
+
+You can also include images in this folder and reference them in the markdown. Each image must be less than
+512 kb in size, and the combined size of all images must be less than 1 MB.
+-->
+
+
+# LATINPRACTICE_2024
+![Logo](https://latinpracticecom.files.wordpress.com/2023/06/logo-lp-2-1.png)
+
+Este proyecto  forma parte de la iniciativa LATINPRACTICE_2024
+con el cual se pretende que profesores universitarios y alumnos de nivel medio superior y superior, tengan acceso a herramientas de software libre para el diseño de circuitos integrados .
+
+Este proyecto es una máquina de estados sencilla que permite controlar el llenado y vaciado automático de un depósito superior de agua alimentado por una bomba conectada a un depósito inferior de agua.
+
+
+## How it works
+El circuito consta de una máquina de estados tipo Mealy con tres estados (Espera, llenado y Alarma).
+
+Las entradas del circuito corresponden a sensores que detectan la presencia o ausencia de agua (1 o 0 lógico), es decir son señales digitales. Un sensor para la cisterna (depósito inferior) y dos sensores para el depósito superior. 
+
+EL circuito cuenta con dos salidas digitales, la primera para encender y apagar la bomba y la segunda para encender una luz o una alarma que indique que no hay agua en el depósito inferior.
+
+El proyecto utiliza un modelo de máquina de estados finitos con tres estados para controlar el llenado del depósito superior mediante una bomba. Los tres estados son:
+
+1. **Espera (`espera`)**: Este estado indica que el sistema está en espera de alguna acción. En este estado, la bomba está apagada (`bomba_o = 0`) y la alarma está desactivada (`alarma_o = 0`). La transición desde este estado ocurre cuando se detecta que el depósito superior está vacío y que hay agua en el depósito inferior (`sensores_i = 001`) o cuando se detecta que la cisterna está llena (`sensores_i = 111`)  o que no hay agua en el depósito inferior (`sensores_i = xx0`) que lo lleva al estado de alarma.
+
+2. **Llenado (`llenado`)**: En este estado, la bomba está encendida (`bomba_o = 1`) para llenar el depósito. La alarma permanece desactivada (`alarma_o = 0`). La transición desde este estado ocurre cuando se detecta que la cisterna está llena (`sensores_i = 111`), lo que indica que el depósito ha alcanzado su capacidad máxima  y regresa al estado de Espera o que no hay agua en el depósito inferior (`sensores_i = xx0`) que lo lleva al estado de alarma.
+
+3. **Alarma (`alarma`)**: Este estado se activa cuando se detecta una condición de alarma, como la falta de agua en el depósito inferior . En este estado, la bomba se apaga (`bomba_o = 0`) y se activa la alarma (`alarma_o = 1`). La transición desde este estado ocurre cuando se detecta que el depósito inferior está lleno (`sensores_i = XX1`), lo que indica que se ha resuelto la condición de alarma.
+
+Cada estado y transición está definido en el código Verilog proporcionado, lo que permite controlar el llenado del depósito mediante la activación y desactivación de la bomba en respuesta a las lecturas de los sensores.
+
+
+
+## How to test
+
+TODO
+
+
+## External hardware
+La asignación de entradas y salidas del diseño del control de la bomba a las entradas y salidas del proyecto Latinpractice son como se indica a continuación.
+
+ck:       Conectado a   uio_in[7].
+rst_i:    Conectado a   uio_in[6].
+sensores_i: Conectado a uio_in[5:3].
+alarma_o: Conectado a uio_out[1].
+bomba_o:  Conectado a uio_out[0].
+
+Como puede notarse, el proyecto de la bomba, para hacer más legible el código, indica cuando un puerto es de entrada colocando un _i al final del nombre del puerto (rst_i) y cuando un puerto es de salida un _o (bomba_o), excepto en el puerto de reloj.
+
+Las entradas de los sensores pueden ser emuladas con botones o con switches conectados a los puertos bidireccionales uio_in[5:3]. Las salidas pueden emularse utilizando LED's conectados a uio_out[0] y uio_out[1] a traveés de una resistencia limitadora de corriente.
+
+## Authors
+
+- [@Arízaga-Silva](https://www.researchgate.net/profile/Juan-Antonio-Arizaga-Silva)
+
+- [@Sanchez-Rincón](https://www.researchgate.net/profile/Ismael_Rincon)
+
+- [@Muñiz-Montero](https://www.researchgate.net/profile/Carlos-Muniz-Montero)

projects/tt_um_bomba1/info.yaml

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+# Tiny Tapeout project information
+project:
+  title:        "Latin_bomba"      # Project title
+  author:       "Arizaga Silva"      # Your name
+  discord:      ""      # Your discord username, for communication and automatically assigning you a Tapeout role (optional)
+  description:  "Circuito de control basado en maquina de estados para controlar el llenado de un deposito de agua a traves de una bomba" # One line description of what your project does
+  language:     "Verilog" # other examples include SystemVerilog, Amaranth, VHDL, etc
+  clock_hz:     0       # Clock frequency in Hz (or 0 if not applicable)
+
+  # How many tiles your design occupies? A single tile is about 167x108 uM.
+  tiles: "1x1"          # Valid values: 1x1, 1x2, 2x2, 3x2, 4x2, 6x2 or 8x2
+
+  # Your top module name must start with "tt_um_". Make it unique by including your github username:
+  top_module:  "tt_um_bomba1"
+
+  # List your project's source files here. Source files must be in ./src and you must list each source file separately, one per line:
+  source_files:        
+    - "tt_um_bomba1.v"
+    - "bomba1.v"
+
+# The pinout of your project. Leave unused pins blank. DO NOT delete or add any pins.
+pinout:
+  # Inputs
+  ui[0]: "no used"
+  ui[1]: "no used"
+  ui[2]: "no used"
+  ui[3]: "no used"
+  ui[4]: "no used"
+  ui[5]: "no used"
+  ui[6]: "no used"
+  ui[7]: "no used"
+
+  # Outputs
+  uo[0]: "no used"
+  uo[1]: "no used"
+  uo[2]: "no used"
+  uo[3]: "no used"
+  uo[4]: "no used"
+  uo[5]: "no used"
+  uo[6]: "no used"
+  uo[7]: "no used"
+
+  # Bidirectional pins
+  uio[0]: "bomba_o"
+  uio[1]: "alarma_o"
+  uio[2]: "no used"
+  uio[3]: "sensores_i[0]"
+  uio[4]: "sensores_i[1]"
+  uio[5]: "sensores_i[2]"
+  uio[6]: "rst_i"
+  uio[7]: "ck"
+
+# Do not change!
+yaml_version: 6

projects/tt_um_bomba1/stats/metrics.csv

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+design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Final_Util,Peak_Memory_Usage_MB,synth_cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,pin_antenna_violations,net_antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,DecapCells,WelltapCells,DiodeCells,FillCells,NonPhysCells,TotalCells,CoreArea_um^2,power_slowest_internal_uW,power_slowest_switching_uW,power_slowest_leakage_uW,power_typical_internal_uW,power_typical_switching_uW,power_typical_leakage_uW,power_fastest_internal_uW,power_fastest_switching_uW,power_fastest_leakage_uW,critical_path_ns,suggested_clock_period,suggested_clock_frequency,CLOCK_PERIOD,FP_ASPECT_RATIO,FP_CORE_UTIL,FP_PDN_HPITCH,FP_PDN_VPITCH,GRT_ADJUSTMENT,GRT_REPAIR_ANTENNAS,MAX_FANOUT_CONSTRAINT,PL_TARGET_DENSITY,RUN_HEURISTIC_DIODE_INSERTION,STD_CELL_LIBRARY,SYNTH_STRATEGY
+/work/src,tt_um_bomba1,wokwi,flow completed,0h0m46s0ms,0h0m31s0ms,5235.392142010569,0.01795472,2617.6960710052845,1.77,3.45168,484.92,42,0,0,0,0,0,0,0,0,0,0,-1,-1,339,210,0.0,-1,-1,-1,-1,0.0,-1,-1,-1,-1,359385.0,0.0,0.65,0.32,0.04,0.0,-1,89,130,15,54,0,0,0,82,1,2,1,2,46,0,0,4,5,6,3,1225,225,0,248,47,1745,16493.3184,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,21.0,47.61904761904762,20,1,50,26.520,38.870,0.3,1,10,0.7,0,sky130_fd_sc_hd,AREA 0