Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Jump to bottom

Revert "New master+wip" #85

Merged
merged 1 commit into from
Jul 6, 2020
Merged

Revert "New master+wip" #85

Show file tree
Hide file tree
Changes from all commits
Commits
Show all changes
1 commit
Select commit
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
The table of contents is too big for display.
Diff view
Diff view
  •  
  •  
  •  
5 changes: 0 additions & 5 deletions .editorconfig
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -5,8 +5,3 @@ indent_style = tab
indent_size = tab
trim_trailing_whitespace = true
insert_final_newline = true

[abc/**]
indent_style = space
indent_size = 2
trim_trailing_whitespace = false
1 change: 0 additions & 1 deletion .gitattributes
View file
Open in desktop

This file was deleted.

1 change: 0 additions & 1 deletion .gitignore
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -21,7 +21,6 @@ __pycache__
/yosys
/yosys.exe
/yosys.js
/yosys.wasm
/yosys-abc
/yosys-abc.exe
/yosys-config
Expand Down
1 change: 0 additions & 1 deletion Brewfile
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -8,4 +8,3 @@ brew "pkg-config"
brew "python3"
brew "tcl-tk"
brew "xdot"
brew "bash"
16 changes: 1 addition & 15 deletions CHANGELOG
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -8,7 +8,7 @@ Yosys 0.9 .. Yosys 0.9-dev

* Various
- Added "write_xaiger" backend
- Added "abc9" pass for timing-aware techmapping (experimental, FPGA only)
- Added "abc9" pass for timing-aware techmapping (experimental, FPGA only, no FFs)
- Added "synth_xilinx -abc9" (experimental)
- Added "synth_ice40 -abc9" (experimental)
- Added "synth -abc9" (experimental)
Expand Down Expand Up @@ -50,23 +50,9 @@ Yosys 0.9 .. Yosys 0.9-dev
- "synth_ecp5" to now infer DSP blocks (-nodsp to disable, experimental)
- "synth_ice40 -dsp" to infer DSP blocks
- Added latch support to synth_xilinx
- Added support for flip-flops with synchronous reset to synth_xilinx
- Added support for flip-flops with reset and enable to synth_xilinx
- Added "check -mapped"
- Added checking of SystemVerilog always block types (always_comb,
always_latch and always_ff)
- Added support for SystemVerilog wildcard port connections (.*)
- Added "xilinx_dffopt" pass
- Added "scratchpad" pass
- Added "synth_xilinx -dff"
- Improved support of $readmem[hb] Memory Content File inclusion
- Added "opt_lut_ins" pass
- Added "logger" pass
- Removed "dffsr2dff" (use opt_rmdff instead)
- Added "design -delete"
- Added "select -unset"
- Use YosysHQ/abc instead of upstream berkeley-abc/abc
- Added $divfloor and $modfloor cells

Yosys 0.8 .. Yosys 0.9
----------------------
Expand Down
37 changes: 0 additions & 37 deletions CODEOWNERS
View file
Open in desktop

This file was deleted.

4 changes: 1 addition & 3 deletions COPYING
View file
Open in desktop
Original file line number Diff line number Diff line change
@@ -1,6 +1,4 @@
ISC License

Copyright (C) 2012 - 2020 Claire Wolf <[email protected]>
Copyright (C) 2012 - 2019 Clifford Wolf <[email protected]>

Permission to use, copy, modify, and/or distribute this software for any
purpose with or without fee is hereby granted, provided that the above
Expand Down
Loading