New master+wip #81
New master+wip #81
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This is an existing invariant (most backends can't cope with these) but one that was not checked or documented.
verilog: Move lexer location variables from global namespace to `VERILOG_FRONTEND` namespace.
Commit ca70a10 did not use a correct check.
ilang_lexer: fix check for out of range literal
qbfsat: Add `-solver` option and allow choice of Z3 or Yices, making Yices the default.
qbfsat: Add support for CVC4.
Restrict RTLIL::IdString to not contain whitespace or control chars
Fix modulo/remainder semantics
…v_logic ast/simplify: don't bitblast async ROMs declared as `logic`
Co-Authored-By: clairexen <[email protected]>
This is basically the same issue as in tests/various/plugin.sh, which uses yosys-config to compile a plugin. `yosys-config --cxxflags` points to `$PREFIX/share/` (/usr/local/share by default), which might not exist yet or might be out of date. Building directly from the headers in ./share/ avoids this.
smtbmc and qbfsat: Add timeout option to set solver timeouts for Z3, Yices, and CVC4.
blackbox: use Module::makeblackbox() method
Clean up `passes/techmap/techmap.cc`
Support asymmetric memories for verific frontend
allow range for mux test
`rewrite_filename` is already called in `Frontend::extra_args`.
techmap: simplify
Signed-off-by: Alessandro Comodi <[email protected]>
Signed-off-by: Keith Rothman <[email protected]>
Signed-off-by: Alessandro Comodi <[email protected]>
Signed-off-by: Alessandro Comodi <[email protected]>
Signed-off-by: Keith Rothman <[email protected]>
Signed-off-by: Alessandro Comodi <[email protected]>
Signed-off-by: Keith Rothman <[email protected]>
Signed-off-by: Keith Rothman <[email protected]>
Signed-off-by: Alessandro Comodi <[email protected]>
Signed-off-by: Alessandro Comodi <[email protected]>
Signed-off-by: Maciej Kurc <[email protected]>
Signed-off-by: Alessandro Comodi <[email protected]>
This enables avoiding the co-mingling of the carry chain port with the ports that connect to the fabric. Signed-off-by: Keith Rothman <[email protected]>
…isable_ramb18e_w2' into new-master+wip
This is an Octopus Merge commit of the following branches: wip/carry4-cout wip/disable-primitives wip/disable_ramb18e_w2 Signed-off-by: Alessandro Comodi <[email protected]>
That's good. At this point, we should probably build a VPR with the latest upstream master + the update to libblifparse (in a wip branch) + a temporary wip branch https://github.com/litghost/vtr-verilog-to-routing/tree/wip/add_back_disable_flag . I expect that VPR should work with current upstream and work with the new yosys master+wip. We can tease out the CPD stuff later. Looking at 1 circuit isn't enough to determine if the new yosys is better or worse, and the new yosys isn't significantly worse.
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Ya, this appears to be a fasm2bels bug. |
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Looks like merging this was a mistake, as failing travis tests prevents the package from being pushed. |
This PR enables a new master+wip for yosys.
Apart from the issues discovered here #79 (comment), there is an additional one which needs to be solved, and is related to the impossibility of setting LOC attributes in the verilog design for primitives (issue open upstream YosysHQ#2176).
This new master+wip version is compatible with this version of symbiflow-arch-defs and
all_xc7tests do pass.The only outstanding issue is solving a problem with Ethernet in the base linux-litex example which is not correctly working on HW.