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--- | ||
title: HDL Explained in 120s | ||
date: 2024-7-21 15:00:00 +0800 | ||
categories: [Tutorials, Zynq] | ||
tags: [fpga, beginner] | ||
pin: false | ||
math: false | ||
mermaid: false | ||
image: | ||
path: https://www.guiahardware.es/wp-content/uploads/2023/08/HDL.jpg | ||
alt: Zynq SoC | ||
--- | ||
# Building your own AXI LED IP | ||
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Based on this [video](https://youtu.be/9wNddNaA_1o). | ||
{% include embed/youtube.html id='9wNddNaA_1o' %} | ||
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> Level : Beginner. | ||
{: .prompt-info } | ||
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## [The repo containing the code from the video](https://github.com/0BAB1/BRH_Tutorials/tree/main/3%20HDL%20-%20A%20system%20verilog%20example) | ||
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## Intro | ||
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HDL is a way to describe hardware and you absolutely need to understand what it does, why, and how to use it in order to move further in your learning journey. | ||
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This video serves as an introduction for beginners to get your head around HDL for the first time and implement your first custom logic through a simple example on Xilinx tools. | ||
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## Prerequisites | ||
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- Know the **basics** of "programming". | ||
- Know what a logic gate and a register is. | ||
- If you want to do the exmaple : Install Vivado. | ||
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> After waching this video, click on the "beginner" tag to check out the other beginners projects tutorial to kickstart you fpga leanrning. | ||
{: .prompt-tip } |
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