fixed prompts

_posts/2024-10-25-FPGA_MANUAL_INFERENCE.md

@@ -13,7 +13,7 @@ image:
 
 # Manual inference : A bonus sub-tutorial
 
->> **This post is a follow up to the ["python to FPGA tutorial"](https://0bab1.github.io/BRH/posts/PY2FPGA/)** . It covers the necessary process to manually implement the output IP from FINN in a design using VIVADO, DMA and many more !
+> **This post is a follow up to the ["python to FPGA tutorial"](https://0bab1.github.io/BRH/posts/PY2FPGA/)** . It covers the necessary process to manually implement the output IP from FINN in a design using VIVADO, DMA and many more !
 {: .prompt-info }
 
 Based on this [video](https://www.youtube.com/watch?v=VsXMlSB6Yq4).
@@ -89,11 +89,8 @@ The end custom system should then look like this :
 
 ![Final system image](https://raw.githubusercontent.com/0BAB1/BRH_Tutorials/refs/heads/main/8%20Python%20to%20FPGA/3_manual_inference/final_custom_system.png)
 
-> [!CAUTION]
-> As you saw in the video, some weird stuff happens when you configure the custom FIFO data width to 32 bits to match the one of DMA. Here's a good way to get around this : 
-> this consits in not changing the default 8bits data width of the fifo and letting the DMA operate in 32 its with memory.
-> To avoid mismatch between the 8bits fifo and the 32bits dma interfaces, we connect them manually using constants and concat blocks, this process is
-> described in the video.
+> As you saw in the video, some weird stuff happens when you configure the custom FIFO data width to 32 bits to match the one of DMA. Here's a good way to get around this : this consits in not changing the default 8bits data width of the fifo and letting the DMA operate in 32 its with memory.To avoid mismatch between the 8bits fifo and the 32bits dma interfaces, we connect them manually using constants and concat blocks. (this process is quilckly described in the video.)
+{: .prompt-danger }
 
 **ANYWAY**, here are the working configs used in the tutorial at the end with the concat and const manual connections :
 

_posts/2024-10-25-PY2FPGA.md

@@ -115,8 +115,8 @@ See you on the other side !
 
 ## Learning resources
 
-> [!IMPORTANT]  
 > Notebooks also contains context-dependant resources to explore and understand important topics.
+{: .prompt-tip }
 
 If you want to truly understand what you are doing and become proficient in engineering, these resources are your go-to.
 

_posts/2024-11-5-Real_time_analysis__for_industrial_engineering.md

@@ -172,6 +172,9 @@ We now have a very interresting tool to determine our worker dedication to a pro
 
 This real time analysis tool was meant for very accurate system, so there is still room for interpretation and tweaking for our application.
 
+> Note that the example given above is just an introduction and only works for simple exmaples were pericicites and cycle times are asseted to be the same for each macine. If this approximation does not fit your use case, contect me for more infrmation on how to accurately estimate the actual line periodicity and thus : worker occupation AND real cylcle time.
+{: .prompt-danger }
+
 This post was meant to introduce the reader to this tool. Similar solutions include the [Cycle diagram](https://fr.wikipedia.org/wiki/Diagramme_de_cycle) which is kind of an old-scool forgetten tool that does not even have an english wiki version.
 
 > If you need clarifications, do not hesitate to contact me, or leave a comment below.

_posts/2024-7-16-Axi_led_ip.md

@@ -71,4 +71,4 @@ Here are some resources to debug AXI interfaces if you'd like to try more advanc
 - [Xilinx AXI VIP as a master to verify your IP](https://support.xilinx.com/s/article/1058302?language=en_US)
 - [Xilinx AXI VIP, use it for your projects & access testbenches](https://www.xilinx.com/video/hardware/how-to-use-axi-verification-ip-to-verify-debug-design-using-simulation.html)
 
-![AXI VIP Img](https://support.xilinx.com/sfc/servlet.shepherd/version/renditionDownload?rendition=THUMB720BY480&versionId=0682E00000SUfk7&operationContext=CHATTER&contentId=05T2E00001lMXoT&page=0)
+![AXI VIP Img](https://support.xilinx.com/sfc/servlet.shepherd/version/renditionDownload?rendition=THUMB720BY480&versionId=0682E00000SUfk7&operationContext=CHATTER&contentId=05T2E00001lMXoT&page=0)

_posts/2024-7-7-Zynq_in_120s.md

@@ -13,7 +13,7 @@ image:
 # Understanding Zynq in 2 minutes
 
 > This post serves as an intro to anyone seeking to learn more on Zynq and FPGA, I encourage you to read it to get started on a learning journey.
-> {: .prompt-info }
+{: .prompt-info }
 
 Based on this [video](https://youtu.be/DQHTSelupDs).
 {% include embed/youtube.html id='DQHTSelupDs' %}
@@ -48,7 +48,7 @@ You are @ the right place !
 ## What now ?
 
 > Where does one get started ?
-> {: .prompt-info }
+{: .prompt-info }
 
 Well there is ne way to get started per say. Learning FPGA is kinda hard sometimes and it is my goal to make it easier.
 
@@ -61,6 +61,7 @@ These are my first few videos, there is probably more to look at now, have a loo
 For each video will be an associated post on this blog, you can find a link to the post in the video description (*and a link to the repo in the post*).
 
 > Most videos I make comes with a hands-on tutorial. Each post (including this one) will have a link to the associated **Github** at the very beginning and some resources at the end.
+{: .prompt-tip }
 
 ## Resources