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Fix stack pointer in core dumps #76221
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Marking as draft because it needs more logic - the size of the Exception Stack Frame depends on whether or not floating-point instructions were used by the faulting thread: https://developer.arm.com/documentation/107706/0100/Floating-point-and-MVE-support/Floating-point-context-handling-mechanisms?lang=en Bit 4 of |
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This was introduced in ff1a5e7, which already put the ESF in r0 and the exception reason in r1. Signed-off-by: Armin Brauns <[email protected]>
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The register set in the coredump contains the register values from just before the trap (these are pushed by hardware as the exception stack frame/ESF). Thus, the SP register also needs to point to the stack location from *before* the ESF was pushed; this is obtained by incrementing the address of the ESF by the size of the ESF. The ESF can be of two types[0]: a Basic stack frame or an Extended stack frame (including FPU registers). Bit 4 in EXC_RETURN (stored in lr on exception entry) determines which type is used. Cortex-A/Cortex-R, don't have hardware exception stacking at all, but also no support for coredumps, so the value passed to exc_return is irrelevant. [0]: https://developer.arm.com/documentation/107706/0100/Floating-point-and-MVE-support/Floating-point-context-handling-mechanisms Signed-off-by: Armin Brauns <[email protected]>
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I don't understand the C++ errors ( |
I believe I'm trying to address the same issue here - #73189 |
Hah, indeed, left a review there. |
@ithinuel please take a look |
@arbrauns this needs rebasing. Thanks! |
Fixed by #79622. |
The register set in the coredump contains the register values from just before the trap (these are pushed by hardware as the exception stack frame/ESF). Thus, the SP register also needs to point to the stack location from before the ESF was pushed; this is simply the location of the ESF plus the size of the ESF.