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hal: renesas: ra: Initial support for display controller
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Add commit to support these features:
- Add support for r_glcdc
- Add support for r_icu

Signed-off-by: Danh Doan <[email protected]>
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@thenguyenyf
Danh Doan authored and thenguyenyf committed Nov 27, 2024
1 parent 51c71d7 commit 1ce7f10
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2 changes: 2 additions & 0 deletions drivers/ra/CMakeLists.txt
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Expand Up @@ -55,6 +55,8 @@ zephyr_library_sources_ifdef(CONFIG_USE_RA_FSP_USB_DEVICE
fsp/src/r_usb_device/r_usb_device.c)
zephyr_library_sources_ifdef(CONFIG_USE_RA_FSP_SDHI
fsp/src/r_sdhi/r_sdhi.c)
zephyr_library_sources_ifdef(CONFIG_USE_RA_FSP_DISPLAY
fsp/src/r_glcdc/r_glcdc.c)

if(CONFIG_USE_RA_FSP_SCE)
zephyr_include_directories(
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453 changes: 453 additions & 0 deletions drivers/ra/fsp/inc/api/r_display_api.h
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154 changes: 154 additions & 0 deletions drivers/ra/fsp/inc/api/r_external_irq_api.h
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/*
* Copyright (c) 2020 - 2024 Renesas Electronics Corporation and/or its affiliates
*
* SPDX-License-Identifier: BSD-3-Clause
*/

/*******************************************************************************************************************//**
* @ingroup RENESAS_INPUT_INTERFACES
* @defgroup EXTERNAL_IRQ_API External IRQ Interface
* @brief Interface for detecting external interrupts.
*
* @section EXTERNAL_IRQ_API_Summary Summary
* The External IRQ Interface is for configuring interrupts to fire when a trigger condition is detected on an
* external IRQ pin.
*
*
* @{
**********************************************************************************************************************/

#ifndef R_EXTERNAL_IRQ_API_H
#define R_EXTERNAL_IRQ_API_H

/***********************************************************************************************************************
* Includes
**********************************************************************************************************************/

/* Includes board and MCU related header files. */
#include "bsp_api.h"

/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */
FSP_HEADER

/**********************************************************************************************************************
* Macro definitions
*********************************************************************************************************************/

/*********************************************************************************************************************
* Typedef definitions
*********************************************************************************************************************/

/** Callback function parameter data */
typedef struct st_external_irq_callback_args
{
/** Placeholder for user data. Set in @ref external_irq_api_t::open function in @ref external_irq_cfg_t. */
void const * p_context;
uint32_t channel; ///< The physical hardware channel that caused the interrupt.
} external_irq_callback_args_t;

#ifndef BSP_OVERRIDE_EXTERNAL_IRQ_TRIGGER_T

/** Condition that will trigger an interrupt when detected. */
typedef enum e_external_irq_trigger
{
EXTERNAL_IRQ_TRIG_FALLING = 0, ///< Falling edge trigger
EXTERNAL_IRQ_TRIG_RISING = 1, ///< Rising edge trigger
EXTERNAL_IRQ_TRIG_BOTH_EDGE = 2, ///< Both edges trigger
EXTERNAL_IRQ_TRIG_LEVEL_LOW = 3, ///< Low level trigger
EXTERNAL_IRQ_TRIG_LEVEL_HIGH = 4 ///< High level trigger
} external_irq_trigger_t;
#endif

#ifndef BSP_OVERRIDE_EXTERNAL_IRQ_PCLK_DIV_T

/** External IRQ input pin digital filtering sample clock divisor settings. The digital filter rejects trigger
* conditions that are shorter than 3 periods of the filter clock.
*/
typedef enum e_external_irq_clock_source_div
{
EXTERNAL_IRQ_CLOCK_SOURCE_DIV_1 = 0, ///< Filter using clock source divided by 1
EXTERNAL_IRQ_CLOCK_SOURCE_DIV_8 = 1, ///< Filter using clock source divided by 8
EXTERNAL_IRQ_CLOCK_SOURCE_DIV_32 = 2, ///< Filter using clock source divided by 32
EXTERNAL_IRQ_CLOCK_SOURCE_DIV_64 = 3, ///< Filter using clock source divided by 64
} external_irq_clock_source_div_t;
#endif

/** User configuration structure, used in open function */
typedef struct st_external_irq_cfg
{
uint8_t channel; ///< Hardware channel used.
uint8_t ipl; ///< Interrupt priority
IRQn_Type irq; ///< Interrupt number assigned to this instance
external_irq_trigger_t trigger; ///< Trigger setting.
external_irq_clock_source_div_t clock_source_div; ///< Digital filter clock divisor setting.
bool filter_enable; ///< Digital filter enable/disable setting.

/** Callback provided external input trigger occurs. */
void (* p_callback)(external_irq_callback_args_t * p_args);

/** Placeholder for user data. Passed to the user callback in @ref external_irq_callback_args_t. */
void const * p_context;
void const * p_extend; ///< External IRQ hardware dependent configuration.
} external_irq_cfg_t;

/** External IRQ control block. Allocate an instance specific control block to pass into the external IRQ API calls.
*/
typedef void external_irq_ctrl_t;

/** External interrupt driver structure. External interrupt functions implemented at the HAL layer will follow this API. */
typedef struct st_external_irq_api
{
/** Initial configuration.
*
* @param[out] p_ctrl Pointer to control block. Must be declared by user. Value set here.
* @param[in] p_cfg Pointer to configuration structure. All elements of the structure must be set by user.
*/
fsp_err_t (* open)(external_irq_ctrl_t * const p_ctrl, external_irq_cfg_t const * const p_cfg);

/** Enable callback when an external trigger condition occurs.
*
* @param[in] p_ctrl Control block set in Open call for this external interrupt.
*/
fsp_err_t (* enable)(external_irq_ctrl_t * const p_ctrl);

/** Disable callback when external trigger condition occurs.
*
* @param[in] p_ctrl Control block set in Open call for this external interrupt.
*/
fsp_err_t (* disable)(external_irq_ctrl_t * const p_ctrl);

/**
* Specify callback function and optional context pointer and working memory pointer.
*
* @param[in] p_ctrl Pointer to the External IRQ control block.
* @param[in] p_callback Callback function
* @param[in] p_context Pointer to send to callback function
* @param[in] p_working_memory Pointer to volatile memory where callback structure can be allocated.
* Callback arguments allocated here are only valid during the callback.
*/
fsp_err_t (* callbackSet)(external_irq_ctrl_t * const p_ctrl, void (* p_callback)(external_irq_callback_args_t *),
void const * const p_context, external_irq_callback_args_t * const p_callback_memory);

/** Allow driver to be reconfigured. May reduce power consumption.
*
* @param[in] p_ctrl Control block set in Open call for this external interrupt.
*/
fsp_err_t (* close)(external_irq_ctrl_t * const p_ctrl);
} external_irq_api_t;

/** This structure encompasses everything that is needed to use an instance of this interface. */
typedef struct st_external_irq_instance
{
external_irq_ctrl_t * p_ctrl; ///< Pointer to the control structure for this instance
external_irq_cfg_t const * p_cfg; ///< Pointer to the configuration structure for this instance
external_irq_api_t const * p_api; ///< Pointer to the API structure for this instance
} external_irq_instance_t;

/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */
FSP_FOOTER

/*******************************************************************************************************************//**
* @} (end defgroup EXTERNAL_IRQ_API)
**********************************************************************************************************************/

#endif
229 changes: 229 additions & 0 deletions drivers/ra/fsp/inc/instances/r_glcdc.h
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/*
* Copyright (c) 2020 - 2024 Renesas Electronics Corporation and/or its affiliates
*
* SPDX-License-Identifier: BSD-3-Clause
*/

/*******************************************************************************************************************//**
* @addtogroup GLCDC
* @{
**********************************************************************************************************************/

#ifndef R_GLCDC_H
#define R_GLCDC_H

/***********************************************************************************************************************
* Includes
**********************************************************************************************************************/
#include "bsp_api.h"
#include "r_display_api.h"

/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */
FSP_HEADER

/***********************************************************************************************************************
* Macro definitions
**********************************************************************************************************************/

/***********************************************************************************************************************
* Typedef definitions
**********************************************************************************************************************/

/** Display control block. DO NOT INITIALIZE. */
typedef struct st_glcdc_instance_ctrl
{
display_state_t state; // Status of GLCDC module

/* Parameters to Event processing for display devices */
void (* p_callback)(display_callback_args_t * p_args); // Pointer to callback function
void const * p_context; // Pointer to the higher level device context
const display_cfg_t * p_cfg; // Pointer to initial configurations
} glcdc_instance_ctrl_t;

/** Clock source select */
typedef enum e_glcdc_clk_src
{
GLCDC_CLK_SRC_INTERNAL, ///< Internal
GLCDC_CLK_SRC_EXTERNAL, ///< External
} glcdc_clk_src_t;

/** Clock frequency division ratio */
typedef enum e_glcdc_panel_clk_div
{
GLCDC_PANEL_CLK_DIVISOR_1 = 1, ///< Division Ratio 1/1
GLCDC_PANEL_CLK_DIVISOR_2 = 2, ///< Division Ratio 1/2
GLCDC_PANEL_CLK_DIVISOR_3 = 3, ///< Division Ratio 1/3
GLCDC_PANEL_CLK_DIVISOR_4 = 4, ///< Division Ratio 1/4
GLCDC_PANEL_CLK_DIVISOR_5 = 5, ///< Division Ratio 1/5
GLCDC_PANEL_CLK_DIVISOR_6 = 6, ///< Division Ratio 1/6
GLCDC_PANEL_CLK_DIVISOR_7 = 7, ///< Division Ratio 1/7
GLCDC_PANEL_CLK_DIVISOR_8 = 8, ///< Division Ratio 1/8
GLCDC_PANEL_CLK_DIVISOR_9 = 9, ///< Division Ratio 1/9
GLCDC_PANEL_CLK_DIVISOR_12 = 12, ///< Division Ratio 1/12
GLCDC_PANEL_CLK_DIVISOR_16 = 16, ///< Division Ratio 1/16
GLCDC_PANEL_CLK_DIVISOR_24 = 24, ///< Division Ratio 1/24
GLCDC_PANEL_CLK_DIVISOR_32 = 32, ///< Division Ratio 1/32
} glcdc_panel_clk_div_t;

/** LCD TCON output pin select */
typedef enum e_glcdc_tcon_pin
{
GLCDC_TCON_PIN_NONE = -1, ///< No output
GLCDC_TCON_PIN_0, ///< LCD_TCON0
GLCDC_TCON_PIN_1, ///< LCD_TCON1
GLCDC_TCON_PIN_2, ///< LCD_TCON2
GLCDC_TCON_PIN_3, ///< LCD_TCON3
} glcdc_tcon_pin_t;

/** Bus Arbitration setting */
typedef enum e_glcdc_bus_arbitraion
{
GLCDC_BUS_ARBITRATION_ROUNDROBIN, ///< Round robin
GLCDC_BUS_ARBITRATION_FIX_PRIORITY ///< Fixed
} glcdc_bus_arbitration_t;

/** Correction circuit sequence control */
typedef enum e_glcdc_correction_proc_order
{
GLCDC_CORRECTION_PROC_ORDER_BRIGHTNESS_CONTRAST2GAMMA, ///< Brightness -> contrast -> gamma correction
GLCDC_CORRECTION_PROC_ORDER_GAMMA2BRIGHTNESS_CONTRAST ///< Gamma correction -> brightness -> contrast
} glcdc_correction_proc_order_t;

/** Timing signals for driving the LCD panel */
typedef enum e_glcdc_tcon_signal_select
{
GLCDC_TCON_SIGNAL_SELECT_STVA_VS = 0, ///< STVA/VS
GLCDC_TCON_SIGNAL_SELECT_STVB_VE = 1, ///< STVB/VE
GLCDC_TCON_SIGNAL_SELECT_STHA_HS = 2, ///< STH/SP/HS
GLCDC_TCON_SIGNAL_SELECT_STHB_HE = 3, ///< STB/LP/HE
GLCDC_TCON_SIGNAL_SELECT_DE = 7 ///< DE
} glcdc_tcon_signal_select_t;

/** Clock phase adjustment for serial RGB output */
typedef enum e_glcdc_clut_plane
{
GLCDC_CLUT_PLANE_0 = 0, ///< GLCDC CLUT plane 0
GLCDC_CLUT_PLANE_1 = 1, ///< GLCDC CLUT plane 1
} glcdc_clut_plane_t;

/** Dithering mode */
typedef enum e_glcdc_dithering_mode
{
GLCDC_DITHERING_MODE_TRUNCATE = 0, ///< No dithering (truncate)
GLCDC_DITHERING_MODE_ROUND_OFF = 1, ///< Dithering with round off
GLCDC_DITHERING_MODE_2X2PATTERN = 2, ///< Dithering with 2x2 pattern
GLCDC_DITHERING_MODE_SETTING_MAX
} glcdc_dithering_mode_t;

/** Dithering mode */
typedef enum e_glcdc_dithering_pattern
{
GLCDC_DITHERING_PATTERN_00 = 0, ///< 2x2 pattern '00'
GLCDC_DITHERING_PATTERN_01 = 1, ///< 2x2 pattern '01'
GLCDC_DITHERING_PATTERN_10 = 2, ///< 2x2 pattern '10'
GLCDC_DITHERING_PATTERN_11 = 3, ///< 2x2 pattern '11'
} glcdc_dithering_pattern_t;

/** Output interface format */
typedef enum e_glcdc_input_interface_format
{
GLCDC_INPUT_INTERFACE_FORMAT_RGB565 = 0, ///< Input interface format RGB565
GLCDC_INPUT_INTERFACE_FORMAT_RGB888 = 1, ///< Input interface format RGB888
GLCDC_INPUT_INTERFACE_FORMAT_ARGB1555 = 2, ///< Input interface format ARGB1555
GLCDC_INPUT_INTERFACE_FORMAT_ARGB4444 = 3, ///< Input interface format ARGB4444
GLCDC_INPUT_INTERFACE_FORMAT_ARGB8888 = 4, ///< Input interface format ARGB8888
GLCDC_INPUT_INTERFACE_FORMAT_CLUT8 = 5, ///< Input interface format CLUT8
GLCDC_INPUT_INTERFACE_FORMAT_CLUT4 = 6, ///< Input interface format CLUT4
GLCDC_INPUT_INTERFACE_FORMAT_CLUT1 = 7, ///< Input interface format CLUT1
} glcdc_input_interface_format_t;

/** Output interface format */
typedef enum e_glcdc_output_interface_format
{
GLCDC_OUTPUT_INTERFACE_FORMAT_RGB888 = 0, ///< Output interface format RGB888
GLCDC_OUTPUT_INTERFACE_FORMAT_RGB666 = 1, ///< Output interface format RGB666
GLCDC_OUTPUT_INTERFACE_FORMAT_RGB565 = 2, ///< Output interface format RGB565
GLCDC_OUTPUT_INTERFACE_FORMAT_SERIAL_RGB = 3, ///< Output interface format Serial RGB
} glcdc_output_interface_format_t;

/** Dithering output format */
typedef enum e_glcdc_dithering_output_format
{
GLCDC_DITHERING_OUTPUT_FORMAT_RGB888 = 0, ///< Dithering output format RGB888
GLCDC_DITHERING_OUTPUT_FORMAT_RGB666 = 1, ///< Dithering output format RGB666
GLCDC_DITHERING_OUTPUT_FORMAT_RGB565 = 2, ///< Dithering output format RGB565
} glcdc_dithering_output_format_t;

/** GLCDC hardware specific configuration */
typedef struct st_glcdc_extended_cfg
{
glcdc_tcon_pin_t tcon_hsync; ///< GLCDC TCON output pin select
glcdc_tcon_pin_t tcon_vsync; ///< GLCDC TCON output pin select
glcdc_tcon_pin_t tcon_de; ///< GLCDC TCON output pin select
glcdc_correction_proc_order_t correction_proc_order; ///< Correction control route select
glcdc_clk_src_t clksrc; ///< Clock Source selection
glcdc_panel_clk_div_t clock_div_ratio; ///< Clock divide ratio for dot clock
glcdc_dithering_mode_t dithering_mode; ///< Dithering mode
glcdc_dithering_pattern_t dithering_pattern_A; ///< Dithering pattern A
glcdc_dithering_pattern_t dithering_pattern_B; ///< Dithering pattern B
glcdc_dithering_pattern_t dithering_pattern_C; ///< Dithering pattern C
glcdc_dithering_pattern_t dithering_pattern_D; ///< Dithering pattern D
void * phy_layer; ///< Alternate PHY layer, such as MIPI DSI.
} glcdc_extended_cfg_t;

/* GLCDC hardware specific control block */
typedef struct st_glcdc_ctrl
{
display_coordinate_t back_porch; ///< Zero coordinate for graphics plane(Back porch end)
uint16_t hsize; ///< Horizontal pixel size in a line
uint16_t vsize; ///< Vertical pixel size in a frame
void * p_context; ///< Pointer to the function level device context
// (e.g. display_ctrl_t type data)
} glcdc_ctrl_t;

/**********************************************************************************************************************
* Exported global variables
**********************************************************************************************************************/

/* @cond INC_HEADER_DEFS_SEC */
/* Filled in Interface API structure for this Instance. */
extern const display_api_t g_display_on_glcdc;

/* @endcond */

/**********************************************************************************************************************
* Public APIs
**********************************************************************************************************************/

fsp_err_t R_GLCDC_Open(display_ctrl_t * const p_api_ctrl, display_cfg_t const * const p_cfg);
fsp_err_t R_GLCDC_Close(display_ctrl_t * const p_api_ctrl);
fsp_err_t R_GLCDC_Start(display_ctrl_t * const p_api_ctrl);
fsp_err_t R_GLCDC_Stop(display_ctrl_t * const p_api_ctrl);
fsp_err_t R_GLCDC_LayerChange(display_ctrl_t const * const p_api_ctrl,
display_runtime_cfg_t const * const p_cfg,
display_frame_layer_t layer);
fsp_err_t R_GLCDC_BufferChange(display_ctrl_t const * const p_api_ctrl,
uint8_t * const framebuffer,
display_frame_layer_t layer);
fsp_err_t R_GLCDC_ColorCorrection(display_ctrl_t const * const p_api_ctrl,
display_correction_t const * const p_correction);
fsp_err_t R_GLCDC_ClutUpdate(display_ctrl_t const * const p_api_ctrl,
display_clut_cfg_t const * const p_clut_cfg,
display_frame_layer_t layer);
fsp_err_t R_GLCDC_ClutEdit(display_ctrl_t const * const p_api_ctrl,
display_frame_layer_t layer,
uint8_t index,
uint32_t color);
fsp_err_t R_GLCDC_ColorKeySet(display_ctrl_t const * const p_api_ctrl,
display_colorkeying_layer_t key_cfg,
display_frame_layer_t layer);
fsp_err_t R_GLCDC_StatusGet(display_ctrl_t const * const p_api_ctrl, display_status_t * const status);

/*******************************************************************************************************************//**
* @} (end defgroup GLCDC)
**********************************************************************************************************************/

/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */
FSP_FOOTER

#endif
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