Merge with upstream (#258)

Cargo.toml

@@ -123,6 +123,7 @@ object = { workspace = true, features = ['std'] }
 wasmtime-test-macros = { path = "crates/test-macros" }
 pulley-interpreter = { workspace = true, features = ["disas"] }
 wasmtime-wast-util = { path = 'crates/wast-util' }
+wasm-encoder = { workspace = true }
 
 [target.'cfg(windows)'.dev-dependencies]
 windows-sys = { workspace = true, features = ["Win32_System_Memory"] }

benches/call.rs

@@ -189,9 +189,7 @@ fn bench_host_to_wasm<Params, Results>(
             for (i, param) in params.iter().enumerate() {
                 space[i] = param.to_raw(&mut *store).unwrap();
             }
-            untyped
-                .call_unchecked(&mut *store, space.as_mut_ptr(), space.len())
-                .unwrap();
+            untyped.call_unchecked(&mut *store, &mut space[..]).unwrap();
             for (i, expected) in results.iter().enumerate() {
                 let ty = expected.ty(&store).unwrap();
                 let actual = Val::from_raw(&mut *store, space[i], ty);

cranelift/codegen/Cargo.toml

@@ -128,10 +128,6 @@ souper-harvest = ["souper-ir", "souper-ir/stringify"]
 # Report any ISLE errors in pretty-printed style.
 isle-errors = ["cranelift-isle/fancy-errors"]
 
-# Put ISLE generated files in isle_generated_code/, for easier
-# inspection, rather than inside of target/.
-isle-in-source-tree = []
-
 # Enable tracking how long passes take in Cranelift.
 #
 # Enabled by default.

cranelift/codegen/build.rs

@@ -63,37 +63,24 @@ fn main() {
 
     println!("cargo:rerun-if-changed=build.rs");
 
-    let explicit_isle_dir = &crate_dir.join("isle_generated_code");
-    #[cfg(feature = "isle-in-source-tree")]
-    let isle_dir = explicit_isle_dir;
-    #[cfg(not(feature = "isle-in-source-tree"))]
-    let isle_dir = &out_dir;
-
-    #[cfg(feature = "isle-in-source-tree")]
-    {
-        std::fs::create_dir_all(isle_dir).expect("Could not create ISLE source directory");
-    }
-    #[cfg(not(feature = "isle-in-source-tree"))]
-    {
-        if explicit_isle_dir.is_dir() {
-            eprintln!(concat!(
-                "Error: directory isle_generated_code/ exists but is only used when\n",
-                "`--feature isle-in-source-tree` is specified. To prevent confusion,\n",
-                "this build script requires the directory to be removed when reverting\n",
-                "to the usual generated code in target/. Please delete the directory and\n",
-                "re-run this build.\n",
-            ));
-            std::process::exit(1);
-        }
-    }
+    let isle_dir = if let Ok(path) = std::env::var("ISLE_SOURCE_DIR") {
+        // This will canonicalize any relative path in terms of the
+        // crate root, and will take any absolute path as overriding the
+        // `crate_dir`.
+        crate_dir.join(&path)
+    } else {
+        out_dir.into()
+    };
+
+    std::fs::create_dir_all(&isle_dir).expect("Could not create ISLE source directory");
 
-    if let Err(err) = meta::generate(&isas, &out_dir, isle_dir) {
+    if let Err(err) = meta::generate(&isas, &out_dir, &isle_dir) {
         eprintln!("Error: {err}");
         process::exit(1);
     }
 
     if &std::env::var("SKIP_ISLE").unwrap_or("0".to_string()) != "1" {
-        if let Err(err) = build_isle(crate_dir, isle_dir) {
+        if let Err(err) = build_isle(crate_dir, &isle_dir) {
             eprintln!("Error: {err}");
             process::exit(1);
         }

cranelift/codegen/src/isa/pulley_shared/abi.rs

@@ -807,7 +807,9 @@ fn create_reg_enviroment() -> MachineEnv {
     };
 
     let non_preferred_regs_by_class: [Vec<PReg>; 3] = {
-        let x_registers: Vec<PReg> = (16..32).map(|x| px_reg(x)).collect();
+        let x_registers: Vec<PReg> = (16..XReg::SPECIAL_START)
+            .map(|x| px_reg(x.into()))
+            .collect();
         let f_registers: Vec<PReg> = (16..32).map(|x| pf_reg(x)).collect();
         let v_registers: Vec<PReg> = vec![];
         [x_registers, f_registers, v_registers]

cranelift/codegen/src/isa/pulley_shared/inst/args.rs

@@ -122,6 +122,12 @@ newtype_of_reg!(XReg, WritableXReg, RegClass::Int);
 newtype_of_reg!(FReg, WritableFReg, RegClass::Float);
 newtype_of_reg!(VReg, WritableVReg, RegClass::Vector);
 
+impl XReg {
+    /// Index of the first "special" register, or the end of which registers
+    /// regalloc is allowed to use.
+    pub const SPECIAL_START: u8 = pulley_interpreter::regs::XReg::SPECIAL_START;
+}
+
 pub use super::super::lower::isle::generated_code::ExtKind;
 
 pub use super::super::lower::isle::generated_code::Amode;

cranelift/codegen/src/isa/pulley_shared/inst/emit.rs

@@ -149,7 +149,7 @@ fn pulley_emit<P>(
             let label = sink.defer_trap(*code);
 
             let cur_off = sink.cur_offset();
-            sink.use_label_at_offset(cur_off, label, LabelUse::Jump(3));
+            sink.use_label_at_offset(cur_off + 3, label, LabelUse::Jump(3));
 
             use ir::condcodes::IntCC::*;
             use OperandSize::*;

cranelift/codegen/src/isa/pulley_shared/inst/mod.rs

@@ -309,7 +309,7 @@ where
     type LabelUse = LabelUse;
     type ABIMachineSpec = PulleyMachineDeps<P>;
 
-    const TRAP_OPCODE: &'static [u8] = &[0];
+    const TRAP_OPCODE: &'static [u8] = TRAP_OPCODE;
 
     fn gen_dummy_use(_reg: Reg) -> Self {
         todo!()
@@ -468,6 +468,19 @@ where
     }
 }
 
+const TRAP_OPCODE: &'static [u8] = &[
+    pulley_interpreter::opcode::Opcode::ExtendedOp as u8,
+    ((pulley_interpreter::opcode::ExtendedOpcode::Trap as u16) >> 0) as u8,
+    ((pulley_interpreter::opcode::ExtendedOpcode::Trap as u16) >> 8) as u8,
+];
+
+#[test]
+fn test_trap_encoding() {
+    let mut dst = std::vec::Vec::new();
+    pulley_interpreter::encode::trap(&mut dst);
+    assert_eq!(dst, TRAP_OPCODE);
+}
+
 //=============================================================================
 // Pretty-printing of instructions.
 

cranelift/codegen/src/isa/pulley_shared/lower.isle

@@ -230,3 +230,14 @@
                                  src
                                  ty
                                  flags)))
+
+;;;; Rules for `stack_addr` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+
+(rule (lower (stack_addr stack_slot offset))
+      (lower_stack_addr stack_slot offset))
+
+(decl lower_stack_addr (StackSlot Offset32) XReg)
+(rule (lower_stack_addr stack_slot offset)
+      (let ((dst WritableXReg (temp_writable_xreg))
+            (_ Unit (emit (abi_stackslot_addr dst stack_slot offset))))
+        dst))

cranelift/codegen/src/machinst/lower.rs

@@ -20,7 +20,7 @@ use crate::machinst::{
     VCodeConstants, VCodeInst, ValueRegs, Writable,
 };
 use crate::settings::Flags;
-use crate::{trace, CodegenResult};
+use crate::{trace, CodegenError, CodegenResult};
 use alloc::vec::Vec;
 use cranelift_control::ControlPlane;
 use rustc_hash::{FxHashMap, FxHashSet};
@@ -676,18 +676,21 @@ impl<'func, I: VCodeInst> Lower<'func, I> {
             // or any of its outputs is used.
             if has_side_effect || value_needed {
                 trace!("lowering: inst {}: {}", inst, self.f.dfg.display_inst(inst));
-                let temp_regs = backend.lower(self, inst).unwrap_or_else(|| {
-                    let ty = if self.num_outputs(inst) > 0 {
-                        Some(self.output_ty(inst, 0))
-                    } else {
-                        None
-                    };
-                    panic!(
-                        "should be implemented in ISLE: inst = `{}`, type = `{:?}`",
-                        self.f.dfg.display_inst(inst),
-                        ty
-                    )
-                });
+                let temp_regs = match backend.lower(self, inst) {
+                    Some(regs) => regs,
+                    None => {
+                        let ty = if self.num_outputs(inst) > 0 {
+                            Some(self.output_ty(inst, 0))
+                        } else {
+                            None
+                        };
+                        return Err(CodegenError::Unsupported(format!(
+                            "should be implemented in ISLE: inst = `{}`, type = `{:?}`",
+                            self.f.dfg.display_inst(inst),
+                            ty
+                        )));
+                    }
+                };
 
                 // The ISLE generated code emits its own registers to define the
                 // instruction's lowered values in. However, other instructions