fpga/common/fb4CGg3: Add RX_CLK_FROM_TX configuration parameter to fb…

…4CGg3@VU09P 100G design Signed-off-by: Alex Forencich <[email protected]>
ucsdsysnet · Feb 17, 2024 · fa0b642 · fa0b642
1 parent 9218698
commit fa0b642
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Showing 6 changed files with 46 additions and 3 deletions.
diff --git a/fpga/mqnic/fb4CGg3/fpga_100g/fpga/config.tcl b/fpga/mqnic/fb4CGg3/fpga_100g/fpga/config.tcl
@@ -151,6 +151,7 @@ dict set params AXIS_ETH_TX_FIFO_PIPELINE "4"
 dict set params AXIS_ETH_TX_TS_PIPELINE "4"
 dict set params AXIS_ETH_RX_PIPELINE "4"
 dict set params AXIS_ETH_RX_FIFO_PIPELINE "4"
+dict set params ETH_RX_CLK_FROM_TX "0"
 
 # Statistics counter subsystem
 dict set params STAT_ENABLE "1"

diff --git a/fpga/mqnic/fb4CGg3/fpga_100g/fpga_app_dma_bench/config.tcl b/fpga/mqnic/fb4CGg3/fpga_100g/fpga_app_dma_bench/config.tcl
@@ -151,6 +151,7 @@ dict set params AXIS_ETH_TX_FIFO_PIPELINE "4"
 dict set params AXIS_ETH_TX_TS_PIPELINE "4"
 dict set params AXIS_ETH_RX_PIPELINE "4"
 dict set params AXIS_ETH_RX_FIFO_PIPELINE "4"
+dict set params ETH_RX_CLK_FROM_TX "0"
 
 # Statistics counter subsystem
 dict set params STAT_ENABLE "1"

diff --git a/fpga/mqnic/fb4CGg3/fpga_100g/rtl/fpga.v b/fpga/mqnic/fb4CGg3/fpga_100g/rtl/fpga.v
@@ -129,6 +129,7 @@ module fpga #
     parameter AXIS_ETH_TX_TS_PIPELINE = 4,
     parameter AXIS_ETH_RX_PIPELINE = 4,
     parameter AXIS_ETH_RX_FIFO_PIPELINE = 4,
+    parameter ETH_RX_CLK_FROM_TX = 0,
 
     // Statistics counter subsystem
     parameter STAT_ENABLE = 1,
@@ -955,6 +956,8 @@ wire                           qsfp_0_rx_axis_tvalid_int;
 wire                           qsfp_0_rx_axis_tlast_int;
 wire [80+1-1:0]                qsfp_0_rx_axis_tuser_int;
 
+wire                           qsfp_0_rx_ptp_clk_int;
+wire                           qsfp_0_rx_ptp_rst_int;
 wire [79:0]                    qsfp_0_rx_ptp_time_int;
 
 wire        qsfp_0_drp_clk = clk_125mhz_int;
@@ -1030,6 +1033,7 @@ cmac_gty_wrapper #(
     .AXIS_KEEP_WIDTH(AXIS_ETH_KEEP_WIDTH),
     .TX_SERDES_PIPELINE(0),
     .RX_SERDES_PIPELINE(0),
+    .RX_CLK_FROM_TX(ETH_RX_CLK_FROM_TX),
     .RS_FEC_ENABLE(1)
 )
 qsfp_0_cmac_inst (
@@ -1095,6 +1099,8 @@ qsfp_0_cmac_inst (
     .rx_axis_tlast(qsfp_0_rx_axis_tlast_int),
     .rx_axis_tuser(qsfp_0_rx_axis_tuser_int),
 
+    .rx_ptp_clk(qsfp_0_rx_ptp_clk_int),
+    .rx_ptp_rst(qsfp_0_rx_ptp_rst_int),
     .rx_ptp_time(qsfp_0_rx_ptp_time_int),
 
     .rx_enable(qsfp_0_rx_enable),
@@ -1132,6 +1138,8 @@ wire                           qsfp_1_rx_axis_tvalid_int;
 wire                           qsfp_1_rx_axis_tlast_int;
 wire [80+1-1:0]                qsfp_1_rx_axis_tuser_int;
 
+wire                           qsfp_1_rx_ptp_clk_int;
+wire                           qsfp_1_rx_ptp_rst_int;
 wire [79:0]                    qsfp_1_rx_ptp_time_int;
 
 wire        qsfp_1_drp_clk = clk_125mhz_int;
@@ -1207,6 +1215,7 @@ cmac_gty_wrapper #(
     .AXIS_KEEP_WIDTH(AXIS_ETH_KEEP_WIDTH),
     .TX_SERDES_PIPELINE(0),
     .RX_SERDES_PIPELINE(0),
+    .RX_CLK_FROM_TX(ETH_RX_CLK_FROM_TX),
     .RS_FEC_ENABLE(1)
 )
 qsfp_1_cmac_inst (
@@ -1272,6 +1281,8 @@ qsfp_1_cmac_inst (
     .rx_axis_tlast(qsfp_1_rx_axis_tlast_int),
     .rx_axis_tuser(qsfp_1_rx_axis_tuser_int),
 
+    .rx_ptp_clk(qsfp_1_rx_ptp_clk_int),
+    .rx_ptp_rst(qsfp_1_rx_ptp_rst_int),
     .rx_ptp_time(qsfp_1_rx_ptp_time_int),
 
     .rx_enable(qsfp_1_rx_enable),
@@ -1309,6 +1320,8 @@ wire                           qsfp_2_rx_axis_tvalid_int;
 wire                           qsfp_2_rx_axis_tlast_int;
 wire [80+1-1:0]                qsfp_2_rx_axis_tuser_int;
 
+wire                           qsfp_2_rx_ptp_clk_int;
+wire                           qsfp_2_rx_ptp_rst_int;
 wire [79:0]                    qsfp_2_rx_ptp_time_int;
 
 wire        qsfp_2_drp_clk = clk_125mhz_int;
@@ -1384,6 +1397,7 @@ cmac_gty_wrapper #(
     .AXIS_KEEP_WIDTH(AXIS_ETH_KEEP_WIDTH),
     .TX_SERDES_PIPELINE(0),
     .RX_SERDES_PIPELINE(0),
+    .RX_CLK_FROM_TX(ETH_RX_CLK_FROM_TX),
     .RS_FEC_ENABLE(1)
 )
 qsfp_2_cmac_inst (
@@ -1449,6 +1463,8 @@ qsfp_2_cmac_inst (
     .rx_axis_tlast(qsfp_2_rx_axis_tlast_int),
     .rx_axis_tuser(qsfp_2_rx_axis_tuser_int),
 
+    .rx_ptp_clk(qsfp_2_rx_ptp_clk_int),
+    .rx_ptp_rst(qsfp_2_rx_ptp_rst_int),
     .rx_ptp_time(qsfp_2_rx_ptp_time_int),
 
     .rx_enable(qsfp_2_rx_enable),
@@ -1486,6 +1502,8 @@ wire                           qsfp_3_rx_axis_tvalid_int;
 wire                           qsfp_3_rx_axis_tlast_int;
 wire [80+1-1:0]                qsfp_3_rx_axis_tuser_int;
 
+wire                           qsfp_3_rx_ptp_clk_int;
+wire                           qsfp_3_rx_ptp_rst_int;
 wire [79:0]                    qsfp_3_rx_ptp_time_int;
 
 wire        qsfp_3_drp_clk = clk_125mhz_int;
@@ -1561,6 +1579,7 @@ cmac_gty_wrapper #(
     .AXIS_KEEP_WIDTH(AXIS_ETH_KEEP_WIDTH),
     .TX_SERDES_PIPELINE(0),
     .RX_SERDES_PIPELINE(0),
+    .RX_CLK_FROM_TX(ETH_RX_CLK_FROM_TX),
     .RS_FEC_ENABLE(1)
 )
 qsfp_3_cmac_inst (
@@ -1626,6 +1645,8 @@ qsfp_3_cmac_inst (
     .rx_axis_tlast(qsfp_3_rx_axis_tlast_int),
     .rx_axis_tuser(qsfp_3_rx_axis_tuser_int),
 
+    .rx_ptp_clk(qsfp_3_rx_ptp_clk_int),
+    .rx_ptp_rst(qsfp_3_rx_ptp_rst_int),
     .rx_ptp_time(qsfp_3_rx_ptp_time_int),
 
     .rx_enable(qsfp_3_rx_enable),
@@ -2278,6 +2299,7 @@ fpga_core #(
     .AXIS_ETH_TX_TS_PIPELINE(AXIS_ETH_TX_TS_PIPELINE),
     .AXIS_ETH_RX_PIPELINE(AXIS_ETH_RX_PIPELINE),
     .AXIS_ETH_RX_FIFO_PIPELINE(AXIS_ETH_RX_FIFO_PIPELINE),
+    .ETH_RX_CLK_FROM_TX(ETH_RX_CLK_FROM_TX),
 
     // Statistics counter subsystem
     .STAT_ENABLE(STAT_ENABLE),
@@ -2425,6 +2447,8 @@ core_inst (
     .qsfp_0_rx_axis_tvalid(qsfp_0_rx_axis_tvalid_int),
     .qsfp_0_rx_axis_tlast(qsfp_0_rx_axis_tlast_int),
     .qsfp_0_rx_axis_tuser(qsfp_0_rx_axis_tuser_int),
+    .qsfp_0_rx_ptp_clk(qsfp_0_rx_ptp_clk_int),
+    .qsfp_0_rx_ptp_rst(qsfp_0_rx_ptp_rst_int),
     .qsfp_0_rx_ptp_time(qsfp_0_rx_ptp_time_int),
 
     .qsfp_0_rx_enable(qsfp_0_rx_enable),
@@ -2483,6 +2507,8 @@ core_inst (
     .qsfp_1_rx_axis_tvalid(qsfp_1_rx_axis_tvalid_int),
     .qsfp_1_rx_axis_tlast(qsfp_1_rx_axis_tlast_int),
     .qsfp_1_rx_axis_tuser(qsfp_1_rx_axis_tuser_int),
+    .qsfp_1_rx_ptp_clk(qsfp_1_rx_ptp_clk_int),
+    .qsfp_1_rx_ptp_rst(qsfp_1_rx_ptp_rst_int),
     .qsfp_1_rx_ptp_time(qsfp_1_rx_ptp_time_int),
 
     .qsfp_1_rx_enable(qsfp_1_rx_enable),
@@ -2541,6 +2567,8 @@ core_inst (
     .qsfp_2_rx_axis_tvalid(qsfp_2_rx_axis_tvalid_int),
     .qsfp_2_rx_axis_tlast(qsfp_2_rx_axis_tlast_int),
     .qsfp_2_rx_axis_tuser(qsfp_2_rx_axis_tuser_int),
+    .qsfp_2_rx_ptp_clk(qsfp_2_rx_ptp_clk_int),
+    .qsfp_2_rx_ptp_rst(qsfp_2_rx_ptp_rst_int),
     .qsfp_2_rx_ptp_time(qsfp_2_rx_ptp_time_int),
 
     .qsfp_2_rx_enable(qsfp_2_rx_enable),
@@ -2599,6 +2627,8 @@ core_inst (
     .qsfp_3_rx_axis_tvalid(qsfp_3_rx_axis_tvalid_int),
     .qsfp_3_rx_axis_tlast(qsfp_3_rx_axis_tlast_int),
     .qsfp_3_rx_axis_tuser(qsfp_3_rx_axis_tuser_int),
+    .qsfp_3_rx_ptp_clk(qsfp_3_rx_ptp_clk_int),
+    .qsfp_3_rx_ptp_rst(qsfp_3_rx_ptp_rst_int),
     .qsfp_3_rx_ptp_time(qsfp_3_rx_ptp_time_int),
 
     .qsfp_3_rx_enable(qsfp_3_rx_enable),

diff --git a/fpga/mqnic/fb4CGg3/fpga_100g/rtl/fpga_core.v b/fpga/mqnic/fb4CGg3/fpga_100g/rtl/fpga_core.v
@@ -151,6 +151,7 @@ module fpga_core #
     parameter AXIS_ETH_TX_TS_PIPELINE = 4,
     parameter AXIS_ETH_RX_PIPELINE = 4,
     parameter AXIS_ETH_RX_FIFO_PIPELINE = 4,
+    parameter ETH_RX_CLK_FROM_TX = 0,
 
     // Statistics counter subsystem
     parameter STAT_ENABLE = 1,
@@ -302,6 +303,8 @@ module fpga_core #
     input  wire                               qsfp_0_rx_axis_tlast,
     input  wire [80+1-1:0]                    qsfp_0_rx_axis_tuser,
 
+    input  wire                               qsfp_0_rx_ptp_clk,
+    input  wire                               qsfp_0_rx_ptp_rst,
     output wire [79:0]                        qsfp_0_rx_ptp_time,
 
     output wire                               qsfp_0_rx_enable,
@@ -363,6 +366,8 @@ module fpga_core #
     input  wire                               qsfp_1_rx_axis_tlast,
     input  wire [80+1-1:0]                    qsfp_1_rx_axis_tuser,
 
+    input  wire                               qsfp_1_rx_ptp_clk,
+    input  wire                               qsfp_1_rx_ptp_rst,
     output wire [79:0]                        qsfp_1_rx_ptp_time,
 
     output wire                               qsfp_1_rx_enable,
@@ -424,6 +429,8 @@ module fpga_core #
     input  wire                               qsfp_2_rx_axis_tlast,
     input  wire [80+1-1:0]                    qsfp_2_rx_axis_tuser,
 
+    input  wire                               qsfp_2_rx_ptp_clk,
+    input  wire                               qsfp_2_rx_ptp_rst,
     output wire [79:0]                        qsfp_2_rx_ptp_time,
 
     output wire                               qsfp_2_rx_enable,
@@ -485,6 +492,8 @@ module fpga_core #
     input  wire                               qsfp_3_rx_axis_tlast,
     input  wire [80+1-1:0]                    qsfp_3_rx_axis_tuser,
 
+    input  wire                               qsfp_3_rx_ptp_clk,
+    input  wire                               qsfp_3_rx_ptp_rst,
     output wire [79:0]                        qsfp_3_rx_ptp_time,
 
     output wire                               qsfp_3_rx_enable,
@@ -1230,8 +1239,8 @@ mqnic_port_map_mac_axis_inst (
     .mac_rx_clk({qsfp_3_rx_clk, qsfp_2_rx_clk, qsfp_1_rx_clk, qsfp_0_rx_clk}),
     .mac_rx_rst({qsfp_3_rx_rst, qsfp_2_rx_rst, qsfp_1_rx_rst, qsfp_0_rx_rst}),
 
-    .mac_rx_ptp_clk(4'b0000),
-    .mac_rx_ptp_rst(4'b0000),
+    .mac_rx_ptp_clk({qsfp_3_rx_ptp_clk, qsfp_2_rx_ptp_clk, qsfp_1_rx_ptp_clk, qsfp_0_rx_ptp_clk}),
+    .mac_rx_ptp_rst({qsfp_3_rx_ptp_rst, qsfp_2_rx_ptp_rst, qsfp_1_rx_ptp_rst, qsfp_0_rx_ptp_rst}),
     .mac_rx_ptp_ts_96({qsfp_3_rx_ptp_time[47:0], qsfp_2_rx_ptp_time[47:0], qsfp_1_rx_ptp_time[47:0], qsfp_0_rx_ptp_time[47:0]}),
     .mac_rx_ptp_ts_step(),
 
@@ -1332,7 +1341,7 @@ mqnic_core_pcie_us #(
     .PTP_CLOCK_PIPELINE(PTP_CLOCK_PIPELINE),
     .PTP_CLOCK_CDC_PIPELINE(PTP_CLOCK_CDC_PIPELINE),
     .PTP_SEPARATE_TX_CLOCK(0),
-    .PTP_SEPARATE_RX_CLOCK(0),
+    .PTP_SEPARATE_RX_CLOCK(ETH_RX_CLK_FROM_TX),
     .PTP_PORT_CDC_PIPELINE(PTP_PORT_CDC_PIPELINE),
     .PTP_PEROUT_ENABLE(PTP_PEROUT_ENABLE),
     .PTP_PEROUT_COUNT(PTP_PEROUT_COUNT),

diff --git a/fpga/mqnic/fb4CGg3/fpga_100g/tb/fpga_core/Makefile b/fpga/mqnic/fb4CGg3/fpga_100g/tb/fpga_core/Makefile
@@ -210,6 +210,7 @@ export PARAM_AXIS_ETH_TX_FIFO_PIPELINE := 4
 export PARAM_AXIS_ETH_TX_TS_PIPELINE := 4
 export PARAM_AXIS_ETH_RX_PIPELINE := 4
 export PARAM_AXIS_ETH_RX_FIFO_PIPELINE := 4
+export PARAM_ETH_RX_CLK_FROM_TX := 0
 
 # Statistics counter subsystem
 export PARAM_STAT_ENABLE := 1

diff --git a/fpga/mqnic/fb4CGg3/fpga_100g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/fb4CGg3/fpga_100g/tb/fpga_core/test_fpga_core.py
@@ -769,6 +769,7 @@ def test_fpga_core(request):
     parameters['AXIS_ETH_TX_TS_PIPELINE'] = 4
     parameters['AXIS_ETH_RX_PIPELINE'] = 4
     parameters['AXIS_ETH_RX_FIFO_PIPELINE'] = 4
+    parameters['ETH_RX_CLK_FROM_TX'] = 0
 
     # Statistics counter subsystem
     parameters['STAT_ENABLE'] = 1