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Add support for truncated relative timestamps
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Signed-off-by: Alex Forencich <[email protected]>
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@alexforencich
alexforencich committed Feb 12, 2024
1 parent 8ff8a0b commit 699bb78
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Showing 283 changed files with 1,406 additions and 793 deletions.
3 changes: 2 additions & 1 deletion fpga/app/custom_port_demo/rtl/mqnic_app_block_custom_port_demo.v
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Original file line number Diff line number Diff line change
Expand Up @@ -36,13 +36,14 @@ module mqnic_app_block #
// PTP configuration
parameter PTP_CLK_PERIOD_NS_NUM = 4,
parameter PTP_CLK_PERIOD_NS_DENOM = 1,
parameter PTP_TS_WIDTH = 96,
parameter PTP_PORT_CDC_PIPELINE = 0,
parameter PTP_PEROUT_ENABLE = 0,
parameter PTP_PEROUT_COUNT = 1,

// Interface configuration
parameter PTP_TS_ENABLE = 1,
parameter PTP_TS_FMT_TOD = 1,
parameter PTP_TS_WIDTH = PTP_TS_FMT_TOD ? 96 : 64,
parameter TX_TAG_WIDTH = 16,
parameter MAX_TX_SIZE = 9214,
parameter MAX_RX_SIZE = 9214,
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3 changes: 3 additions & 0 deletions fpga/app/custom_port_demo/tb/mqnic_core_pcie_us/Makefile
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Original file line number Diff line number Diff line change
Expand Up @@ -62,6 +62,7 @@ VERILOG_SOURCES += ../../lib/eth/rtl/mac_pause_ctrl_tx.v
VERILOG_SOURCES += ../../lib/eth/rtl/ptp_td_phc.v
VERILOG_SOURCES += ../../lib/eth/rtl/ptp_td_leaf.v
VERILOG_SOURCES += ../../lib/eth/rtl/ptp_perout.v
VERILOG_SOURCES += ../../lib/eth/rtl/ptp_td_rel2tod.v
VERILOG_SOURCES += ../../lib/axi/rtl/axil_crossbar.v
VERILOG_SOURCES += ../../lib/axi/rtl/axil_crossbar_addr.v
VERILOG_SOURCES += ../../lib/axi/rtl/axil_crossbar_rd.v
Expand Down Expand Up @@ -159,6 +160,8 @@ export PARAM_TDMA_INDEX_WIDTH := 6

# Interface configuration
export PARAM_PTP_TS_ENABLE := 1
export PARAM_PTP_TS_FMT_TOD := 0
export PARAM_PTP_TS_WIDTH := $(if $(filter-out 1,$(PARAM_PTP_TS_FMT_TOD)),48,96)
export PARAM_TX_CPL_ENABLE := $(PARAM_PTP_TS_ENABLE)
export PARAM_TX_CPL_FIFO_DEPTH := 32
export PARAM_TX_TAG_WIDTH := 16
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24 changes: 14 additions & 10 deletions fpga/app/custom_port_demo/tb/mqnic_core_pcie_us/test_mqnic_core_pcie_us.py
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Expand Up @@ -759,18 +759,19 @@ async def run_test_nic(dut):


@pytest.mark.parametrize(("if_count", "ports_per_if", "axis_pcie_data_width",
"axis_eth_data_width", "axis_eth_sync_data_width", "ptp_ts_enable"), [
(1, 1, 256, 64, 64, 1),
(1, 1, 256, 64, 64, 0),
(2, 1, 256, 64, 64, 1),
(1, 2, 256, 64, 64, 1),
(1, 1, 256, 64, 128, 1),
(1, 1, 512, 64, 64, 1),
(1, 1, 512, 64, 128, 1),
(1, 1, 512, 512, 512, 1),
"axis_eth_data_width", "axis_eth_sync_data_width", "ptp_ts_enable", "ptp_ts_fmt_tod"), [
(1, 1, 256, 64, 64, 1, 0),
(1, 1, 256, 64, 64, 1, 1),
(1, 1, 256, 64, 64, 0, 0),
(2, 1, 256, 64, 64, 1, 0),
(1, 2, 256, 64, 64, 1, 0),
(1, 1, 256, 64, 128, 1, 0),
(1, 1, 512, 64, 64, 1, 0),
(1, 1, 512, 64, 128, 1, 0),
(1, 1, 512, 512, 512, 1, 0),
])
def test_mqnic_core_pcie_us(request, if_count, ports_per_if, axis_pcie_data_width,
axis_eth_data_width, axis_eth_sync_data_width, ptp_ts_enable):
axis_eth_data_width, axis_eth_sync_data_width, ptp_ts_enable, ptp_ts_fmt_tod):
dut = "mqnic_core_pcie_us"
module = os.path.splitext(os.path.basename(__file__))[0]
toplevel = dut
Expand Down Expand Up @@ -828,6 +829,7 @@ def test_mqnic_core_pcie_us(request, if_count, ports_per_if, axis_pcie_data_widt
os.path.join(eth_rtl_dir, "mac_pause_ctrl_tx.v"),
os.path.join(eth_rtl_dir, "ptp_td_phc.v"),
os.path.join(eth_rtl_dir, "ptp_td_leaf.v"),
os.path.join(eth_rtl_dir, "ptp_td_rel2tod.v"),
os.path.join(eth_rtl_dir, "ptp_perout.v"),
os.path.join(axi_rtl_dir, "axil_crossbar.v"),
os.path.join(axi_rtl_dir, "axil_crossbar_addr.v"),
Expand Down Expand Up @@ -928,6 +930,8 @@ def test_mqnic_core_pcie_us(request, if_count, ports_per_if, axis_pcie_data_widt

# Interface configuration
parameters['PTP_TS_ENABLE'] = ptp_ts_enable
parameters['PTP_TS_FMT_TOD'] = ptp_ts_fmt_tod
parameters['PTP_TS_WIDTH'] = 96 if parameters['PTP_TS_FMT_TOD'] else 48
parameters['TX_CPL_ENABLE'] = parameters['PTP_TS_ENABLE']
parameters['TX_CPL_FIFO_DEPTH'] = 32
parameters['TX_TAG_WIDTH'] = 16
Expand Down
3 changes: 2 additions & 1 deletion fpga/app/dma_bench/rtl/mqnic_app_block_dma_bench.v
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Original file line number Diff line number Diff line change
Expand Up @@ -28,13 +28,14 @@ module mqnic_app_block #
// PTP configuration
parameter PTP_CLK_PERIOD_NS_NUM = 4,
parameter PTP_CLK_PERIOD_NS_DENOM = 1,
parameter PTP_TS_WIDTH = 96,
parameter PTP_PORT_CDC_PIPELINE = 0,
parameter PTP_PEROUT_ENABLE = 0,
parameter PTP_PEROUT_COUNT = 1,

// Interface configuration
parameter PTP_TS_ENABLE = 1,
parameter PTP_TS_FMT_TOD = 1,
parameter PTP_TS_WIDTH = PTP_TS_FMT_TOD ? 96 : 64,
parameter TX_TAG_WIDTH = 16,
parameter MAX_TX_SIZE = 9214,
parameter MAX_RX_SIZE = 9214,
Expand Down
3 changes: 3 additions & 0 deletions fpga/app/dma_bench/tb/mqnic_core_pcie_us/Makefile
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Original file line number Diff line number Diff line change
Expand Up @@ -63,6 +63,7 @@ VERILOG_SOURCES += ../../lib/eth/rtl/mac_pause_ctrl_tx.v
VERILOG_SOURCES += ../../lib/eth/rtl/ptp_td_phc.v
VERILOG_SOURCES += ../../lib/eth/rtl/ptp_td_leaf.v
VERILOG_SOURCES += ../../lib/eth/rtl/ptp_perout.v
VERILOG_SOURCES += ../../lib/eth/rtl/ptp_td_rel2tod.v
VERILOG_SOURCES += ../../lib/eth/rtl/lfsr.v
VERILOG_SOURCES += ../../lib/axi/rtl/axi_vfifo_raw.v
VERILOG_SOURCES += ../../lib/axi/rtl/axi_vfifo_raw_rd.v
Expand Down Expand Up @@ -164,6 +165,8 @@ export PARAM_TDMA_INDEX_WIDTH := 6

# Interface configuration
export PARAM_PTP_TS_ENABLE := 1
export PARAM_PTP_TS_FMT_TOD := 0
export PARAM_PTP_TS_WIDTH := $(if $(filter-out 1,$(PARAM_PTP_TS_FMT_TOD)),48,96)
export PARAM_TX_CPL_ENABLE := $(PARAM_PTP_TS_ENABLE)
export PARAM_TX_CPL_FIFO_DEPTH := 32
export PARAM_TX_TAG_WIDTH := 16
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24 changes: 14 additions & 10 deletions fpga/app/dma_bench/tb/mqnic_core_pcie_us/test_mqnic_core_pcie_us.py
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Original file line number Diff line number Diff line change
Expand Up @@ -950,18 +950,19 @@ async def run_test_nic(dut):


@pytest.mark.parametrize(("if_count", "ports_per_if", "axis_pcie_data_width",
"axis_eth_data_width", "axis_eth_sync_data_width", "ptp_ts_enable"), [
(1, 1, 256, 64, 64, 1),
(1, 1, 256, 64, 64, 0),
(2, 1, 256, 64, 64, 1),
(1, 2, 256, 64, 64, 1),
(1, 1, 256, 64, 128, 1),
(1, 1, 512, 64, 64, 1),
(1, 1, 512, 64, 128, 1),
(1, 1, 512, 512, 512, 1),
"axis_eth_data_width", "axis_eth_sync_data_width", "ptp_ts_enable", "ptp_ts_fmt_tod"), [
(1, 1, 256, 64, 64, 1, 0),
(1, 1, 256, 64, 64, 1, 1),
(1, 1, 256, 64, 64, 0, 0),
(2, 1, 256, 64, 64, 1, 0),
(1, 2, 256, 64, 64, 1, 0),
(1, 1, 256, 64, 128, 1, 0),
(1, 1, 512, 64, 64, 1, 0),
(1, 1, 512, 64, 128, 1, 0),
(1, 1, 512, 512, 512, 1, 0),
])
def test_mqnic_core_pcie_us(request, if_count, ports_per_if, axis_pcie_data_width,
axis_eth_data_width, axis_eth_sync_data_width, ptp_ts_enable):
axis_eth_data_width, axis_eth_sync_data_width, ptp_ts_enable, ptp_ts_fmt_tod):
dut = "mqnic_core_pcie_us"
module = os.path.splitext(os.path.basename(__file__))[0]
toplevel = dut
Expand Down Expand Up @@ -1017,6 +1018,7 @@ def test_mqnic_core_pcie_us(request, if_count, ports_per_if, axis_pcie_data_widt
os.path.join(eth_rtl_dir, "mac_pause_ctrl_tx.v"),
os.path.join(eth_rtl_dir, "ptp_td_phc.v"),
os.path.join(eth_rtl_dir, "ptp_td_leaf.v"),
os.path.join(eth_rtl_dir, "ptp_td_rel2tod.v"),
os.path.join(eth_rtl_dir, "ptp_perout.v"),
os.path.join(eth_rtl_dir, "lfsr.v"),
os.path.join(axi_rtl_dir, "axi_vfifo_raw.v"),
Expand Down Expand Up @@ -1119,6 +1121,8 @@ def test_mqnic_core_pcie_us(request, if_count, ports_per_if, axis_pcie_data_widt

# Interface configuration
parameters['PTP_TS_ENABLE'] = ptp_ts_enable
parameters['PTP_TS_FMT_TOD'] = ptp_ts_fmt_tod
parameters['PTP_TS_WIDTH'] = 96 if parameters['PTP_TS_FMT_TOD'] else 48
parameters['TX_CPL_ENABLE'] = parameters['PTP_TS_ENABLE']
parameters['TX_CPL_FIFO_DEPTH'] = 32
parameters['TX_TAG_WIDTH'] = 16
Expand Down
3 changes: 2 additions & 1 deletion fpga/app/template/rtl/mqnic_app_block.v
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Original file line number Diff line number Diff line change
Expand Up @@ -36,13 +36,14 @@ module mqnic_app_block #
// PTP configuration
parameter PTP_CLK_PERIOD_NS_NUM = 4,
parameter PTP_CLK_PERIOD_NS_DENOM = 1,
parameter PTP_TS_WIDTH = 96,
parameter PTP_PORT_CDC_PIPELINE = 0,
parameter PTP_PEROUT_ENABLE = 0,
parameter PTP_PEROUT_COUNT = 1,

// Interface configuration
parameter PTP_TS_ENABLE = 1,
parameter PTP_TS_FMT_TOD = 1,
parameter PTP_TS_WIDTH = PTP_TS_FMT_TOD ? 96 : 64,
parameter TX_TAG_WIDTH = 16,
parameter MAX_TX_SIZE = 9214,
parameter MAX_RX_SIZE = 9214,
Expand Down
3 changes: 3 additions & 0 deletions fpga/app/template/tb/mqnic_core_pcie_us/Makefile
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Original file line number Diff line number Diff line change
Expand Up @@ -60,6 +60,7 @@ VERILOG_SOURCES += ../../lib/eth/rtl/mac_pause_ctrl_rx.v
VERILOG_SOURCES += ../../lib/eth/rtl/mac_pause_ctrl_tx.v
VERILOG_SOURCES += ../../lib/eth/rtl/ptp_td_phc.v
VERILOG_SOURCES += ../../lib/eth/rtl/ptp_td_leaf.v
VERILOG_SOURCES += ../../lib/eth/rtl/ptp_td_rel2tod.v
VERILOG_SOURCES += ../../lib/eth/rtl/ptp_perout.v
VERILOG_SOURCES += ../../lib/axi/rtl/axil_crossbar.v
VERILOG_SOURCES += ../../lib/axi/rtl/axil_crossbar_addr.v
Expand Down Expand Up @@ -158,6 +159,8 @@ export PARAM_TDMA_INDEX_WIDTH := 6

# Interface configuration
export PARAM_PTP_TS_ENABLE := 1
export PARAM_PTP_TS_FMT_TOD := 0
export PARAM_PTP_TS_WIDTH := $(if $(filter-out 1,$(PARAM_PTP_TS_FMT_TOD)),48,96)
export PARAM_TX_CPL_ENABLE := $(PARAM_PTP_TS_ENABLE)
export PARAM_TX_CPL_FIFO_DEPTH := 32
export PARAM_TX_TAG_WIDTH := 16
Expand Down
24 changes: 14 additions & 10 deletions fpga/app/template/tb/mqnic_core_pcie_us/test_mqnic_core_pcie_us.py
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Original file line number Diff line number Diff line change
Expand Up @@ -753,18 +753,19 @@ async def run_test_nic(dut):


@pytest.mark.parametrize(("if_count", "ports_per_if", "axis_pcie_data_width",
"axis_eth_data_width", "axis_eth_sync_data_width", "ptp_ts_enable"), [
(1, 1, 256, 64, 64, 1),
(1, 1, 256, 64, 64, 0),
(2, 1, 256, 64, 64, 1),
(1, 2, 256, 64, 64, 1),
(1, 1, 256, 64, 128, 1),
(1, 1, 512, 64, 64, 1),
(1, 1, 512, 64, 128, 1),
(1, 1, 512, 512, 512, 1),
"axis_eth_data_width", "axis_eth_sync_data_width", "ptp_ts_enable", "ptp_ts_fmt_tod"), [
(1, 1, 256, 64, 64, 1, 0),
(1, 1, 256, 64, 64, 1, 1),
(1, 1, 256, 64, 64, 0, 0),
(2, 1, 256, 64, 64, 1, 0),
(1, 2, 256, 64, 64, 1, 0),
(1, 1, 256, 64, 128, 1, 0),
(1, 1, 512, 64, 64, 1, 0),
(1, 1, 512, 64, 128, 1, 0),
(1, 1, 512, 512, 512, 1, 0),
])
def test_mqnic_core_pcie_us(request, if_count, ports_per_if, axis_pcie_data_width,
axis_eth_data_width, axis_eth_sync_data_width, ptp_ts_enable):
axis_eth_data_width, axis_eth_sync_data_width, ptp_ts_enable, ptp_ts_fmt_tod):
dut = "mqnic_core_pcie_us"
module = os.path.splitext(os.path.basename(__file__))[0]
toplevel = dut
Expand Down Expand Up @@ -818,6 +819,7 @@ def test_mqnic_core_pcie_us(request, if_count, ports_per_if, axis_pcie_data_widt
os.path.join(eth_rtl_dir, "mac_pause_ctrl_tx.v"),
os.path.join(eth_rtl_dir, "ptp_td_phc.v"),
os.path.join(eth_rtl_dir, "ptp_td_leaf.v"),
os.path.join(eth_rtl_dir, "ptp_td_rel2tod.v"),
os.path.join(eth_rtl_dir, "ptp_perout.v"),
os.path.join(axi_rtl_dir, "axil_crossbar.v"),
os.path.join(axi_rtl_dir, "axil_crossbar_addr.v"),
Expand Down Expand Up @@ -917,6 +919,8 @@ def test_mqnic_core_pcie_us(request, if_count, ports_per_if, axis_pcie_data_widt

# Interface configuration
parameters['PTP_TS_ENABLE'] = ptp_ts_enable
parameters['PTP_TS_FMT_TOD'] = ptp_ts_fmt_tod
parameters['PTP_TS_WIDTH'] = 96 if parameters['PTP_TS_FMT_TOD'] else 48
parameters['TX_CPL_ENABLE'] = parameters['PTP_TS_ENABLE']
parameters['TX_CPL_FIFO_DEPTH'] = 32
parameters['TX_TAG_WIDTH'] = 16
Expand Down
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