fpga/mqnic: Normalize RAM size settings

Signed-off-by: Alex Forencich <[email protected]>
ucsdsysnet · Feb 22, 2024 · 0f1dfcf · 0f1dfcf
1 parent 49db485
commit 0f1dfcf
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Showing 49 changed files with 55 additions and 55 deletions.
diff --git a/fpga/mqnic/250_SoC/fpga_25g/tb/fpga_core/Makefile b/fpga/mqnic/250_SoC/fpga_25g/tb/fpga_core/Makefile
@@ -174,7 +174,7 @@ export PARAM_RX_CHECKSUM_ENABLE := 1
 export PARAM_LFC_ENABLE := 1
 export PARAM_PFC_ENABLE := $(PARAM_LFC_ENABLE)
 export PARAM_TX_FIFO_DEPTH := 32768
-export PARAM_RX_FIFO_DEPTH := 32768
+export PARAM_RX_FIFO_DEPTH := 65536
 export PARAM_MAX_TX_SIZE := 9214
 export PARAM_MAX_RX_SIZE := 9214
 export PARAM_TX_RAM_SIZE := 32768

diff --git a/fpga/mqnic/250_SoC/fpga_25g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/250_SoC/fpga_25g/tb/fpga_core/test_fpga_core.py
@@ -832,7 +832,7 @@ def test_fpga_core(request):
     parameters['LFC_ENABLE'] = 1
     parameters['PFC_ENABLE'] = parameters['LFC_ENABLE']
     parameters['TX_FIFO_DEPTH'] = 32768
-    parameters['RX_FIFO_DEPTH'] = 32768
+    parameters['RX_FIFO_DEPTH'] = 65536
     parameters['MAX_TX_SIZE'] = 9214
     parameters['MAX_RX_SIZE'] = 9214
     parameters['TX_RAM_SIZE'] = 32768

diff --git a/fpga/mqnic/520N_MX/fpga_25g/tb/fpga_core/Makefile b/fpga/mqnic/520N_MX/fpga_25g/tb/fpga_core/Makefile
@@ -172,7 +172,7 @@ export PARAM_RX_CHECKSUM_ENABLE := 1
 export PARAM_LFC_ENABLE := 1
 export PARAM_PFC_ENABLE := $(PARAM_LFC_ENABLE)
 export PARAM_TX_FIFO_DEPTH := 32768
-export PARAM_RX_FIFO_DEPTH := 32768
+export PARAM_RX_FIFO_DEPTH := 65536
 export PARAM_MAX_TX_SIZE := 9214
 export PARAM_MAX_RX_SIZE := 9214
 export PARAM_TX_RAM_SIZE := 32768

diff --git a/fpga/mqnic/520N_MX/fpga_25g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/520N_MX/fpga_25g/tb/fpga_core/test_fpga_core.py
@@ -740,7 +740,7 @@ def test_fpga_core(request):
     parameters['LFC_ENABLE'] = 1
     parameters['PFC_ENABLE'] = parameters['LFC_ENABLE']
     parameters['TX_FIFO_DEPTH'] = 32768
-    parameters['RX_FIFO_DEPTH'] = 32768
+    parameters['RX_FIFO_DEPTH'] = 65536
     parameters['MAX_TX_SIZE'] = 9214
     parameters['MAX_RX_SIZE'] = 9214
     parameters['TX_RAM_SIZE'] = 32768

diff --git a/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga_tdma/config.tcl b/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga_tdma/config.tcl
@@ -120,7 +120,7 @@ dict set params ENABLE_PADDING "1"
 dict set params ENABLE_DIC "1"
 dict set params MIN_FRAME_LENGTH "64"
 dict set params TX_FIFO_DEPTH "32768"
-dict set params RX_FIFO_DEPTH "32768"
+dict set params RX_FIFO_DEPTH "65536"
 dict set params MAX_TX_SIZE "9214"
 dict set params MAX_RX_SIZE "9214"
 dict set params TX_RAM_SIZE "32768"

diff --git a/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/tb/fpga_core/Makefile b/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/tb/fpga_core/Makefile
@@ -175,7 +175,7 @@ export PARAM_RX_CHECKSUM_ENABLE := 1
 export PARAM_LFC_ENABLE := 1
 export PARAM_PFC_ENABLE := $(PARAM_LFC_ENABLE)
 export PARAM_TX_FIFO_DEPTH := 32768
-export PARAM_RX_FIFO_DEPTH := 32768
+export PARAM_RX_FIFO_DEPTH := 65536
 export PARAM_MAX_TX_SIZE := 9214
 export PARAM_MAX_RX_SIZE := 9214
 export PARAM_TX_RAM_SIZE := 32768

diff --git a/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/tb/fpga_core/test_fpga_core.py
@@ -835,7 +835,7 @@ def test_fpga_core(request):
     parameters['LFC_ENABLE'] = 1
     parameters['PFC_ENABLE'] = parameters['LFC_ENABLE']
     parameters['TX_FIFO_DEPTH'] = 32768
-    parameters['RX_FIFO_DEPTH'] = 32768
+    parameters['RX_FIFO_DEPTH'] = 65536
     parameters['MAX_TX_SIZE'] = 9214
     parameters['MAX_RX_SIZE'] = 9214
     parameters['TX_RAM_SIZE'] = 32768

diff --git a/fpga/mqnic/Alveo/fpga_25g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/Alveo/fpga_25g/tb/fpga_core/test_fpga_core.py
@@ -832,7 +832,7 @@ def test_fpga_core(request, qsfp_cnt, if_cnt, ports_per_if, sched_per_if):
     parameters['LFC_ENABLE'] = 1
     parameters['PFC_ENABLE'] = parameters['LFC_ENABLE']
     parameters['TX_FIFO_DEPTH'] = 32768
-    parameters['RX_FIFO_DEPTH'] = 32768
+    parameters['RX_FIFO_DEPTH'] = 65536
     parameters['MAX_TX_SIZE'] = 9214
     parameters['MAX_RX_SIZE'] = 9214
     parameters['TX_RAM_SIZE'] = 32768

diff --git a/fpga/mqnic/DE10_Agilex/fpga_100g/fpga_25g/config.tcl b/fpga/mqnic/DE10_Agilex/fpga_100g/fpga_25g/config.tcl
@@ -111,7 +111,7 @@ dict set params RX_FIFO_DEPTH "65536"
 dict set params MAX_TX_SIZE "9214"
 dict set params MAX_RX_SIZE "9214"
 dict set params TX_RAM_SIZE "32768"
-dict set params RX_RAM_SIZE "32768"
+dict set params RX_RAM_SIZE "131072"
 
 # Application block configuration
 dict set params APP_ID "32'h00000000"

diff --git a/fpga/mqnic/DE10_Agilex/fpga_100g/fpga_25g_24AR0/config.tcl b/fpga/mqnic/DE10_Agilex/fpga_100g/fpga_25g_24AR0/config.tcl
@@ -111,7 +111,7 @@ dict set params RX_FIFO_DEPTH "65536"
 dict set params MAX_TX_SIZE "9214"
 dict set params MAX_RX_SIZE "9214"
 dict set params TX_RAM_SIZE "32768"
-dict set params RX_RAM_SIZE "32768"
+dict set params RX_RAM_SIZE "131072"
 
 # Application block configuration
 dict set params APP_ID "32'h00000000"

diff --git a/fpga/mqnic/DK_DEV_1SMX_H_A/fpga_25g/fpga_1sm21b/config.tcl b/fpga/mqnic/DK_DEV_1SMX_H_A/fpga_25g/fpga_1sm21b/config.tcl
@@ -114,7 +114,7 @@ dict set params RX_FIFO_DEPTH "65536"
 dict set params MAX_TX_SIZE "9214"
 dict set params MAX_RX_SIZE "9214"
 dict set params TX_RAM_SIZE "32768"
-dict set params RX_RAM_SIZE "32768"
+dict set params RX_RAM_SIZE "131072"
 
 # Application block configuration
 dict set params APP_ID "32'h00000000"

diff --git a/fpga/mqnic/DK_DEV_1SMX_H_A/fpga_25g/fpga_1sm21c/config.tcl b/fpga/mqnic/DK_DEV_1SMX_H_A/fpga_25g/fpga_1sm21c/config.tcl
@@ -114,7 +114,7 @@ dict set params RX_FIFO_DEPTH "65536"
 dict set params MAX_TX_SIZE "9214"
 dict set params MAX_RX_SIZE "9214"
 dict set params TX_RAM_SIZE "32768"
-dict set params RX_RAM_SIZE "32768"
+dict set params RX_RAM_SIZE "131072"
 
 # Application block configuration
 dict set params APP_ID "32'h00000000"

diff --git a/fpga/mqnic/DK_DEV_1SMX_H_A/fpga_25g/tb/fpga_core/Makefile b/fpga/mqnic/DK_DEV_1SMX_H_A/fpga_25g/tb/fpga_core/Makefile
@@ -173,11 +173,11 @@ export PARAM_RX_CHECKSUM_ENABLE := 1
 export PARAM_LFC_ENABLE := 1
 export PARAM_PFC_ENABLE := $(PARAM_LFC_ENABLE)
 export PARAM_TX_FIFO_DEPTH := 32768
-export PARAM_RX_FIFO_DEPTH := 32768
+export PARAM_RX_FIFO_DEPTH := 65536
 export PARAM_MAX_TX_SIZE := 9214
 export PARAM_MAX_RX_SIZE := 9214
 export PARAM_TX_RAM_SIZE := 32768
-export PARAM_RX_RAM_SIZE := 32768
+export PARAM_RX_RAM_SIZE := 131072
 
 # Application block configuration
 export PARAM_APP_ID := $(shell echo $$((0x00000000)) )

diff --git a/fpga/mqnic/DK_DEV_1SMX_H_A/fpga_25g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/DK_DEV_1SMX_H_A/fpga_25g/tb/fpga_core/test_fpga_core.py
@@ -743,11 +743,11 @@ def test_fpga_core(request):
     parameters['LFC_ENABLE'] = 1
     parameters['PFC_ENABLE'] = parameters['LFC_ENABLE']
     parameters['TX_FIFO_DEPTH'] = 32768
-    parameters['RX_FIFO_DEPTH'] = 32768
+    parameters['RX_FIFO_DEPTH'] = 65536
     parameters['MAX_TX_SIZE'] = 9214
     parameters['MAX_RX_SIZE'] = 9214
     parameters['TX_RAM_SIZE'] = 32768
-    parameters['RX_RAM_SIZE'] = 32768
+    parameters['RX_RAM_SIZE'] = 131072
 
     # Application block configuration
     parameters['APP_ID'] = 0x00000000

diff --git a/fpga/mqnic/DK_DEV_AGF014EA/fpga_100g/fpga_25g/config.tcl b/fpga/mqnic/DK_DEV_AGF014EA/fpga_100g/fpga_25g/config.tcl
@@ -111,7 +111,7 @@ dict set params RX_FIFO_DEPTH "65536"
 dict set params MAX_TX_SIZE "9214"
 dict set params MAX_RX_SIZE "9214"
 dict set params TX_RAM_SIZE "32768"
-dict set params RX_RAM_SIZE "32768"
+dict set params RX_RAM_SIZE "131072"
 
 # Application block configuration
 dict set params APP_ID "32'h00000000"

diff --git a/fpga/mqnic/DK_DEV_AGF014EA/fpga_100g/fpga_25g_24AR0/config.tcl b/fpga/mqnic/DK_DEV_AGF014EA/fpga_100g/fpga_25g_24AR0/config.tcl
@@ -111,7 +111,7 @@ dict set params RX_FIFO_DEPTH "65536"
 dict set params MAX_TX_SIZE "9214"
 dict set params MAX_RX_SIZE "9214"
 dict set params TX_RAM_SIZE "32768"
-dict set params RX_RAM_SIZE "32768"
+dict set params RX_RAM_SIZE "131072"
 
 # Application block configuration
 dict set params APP_ID "32'h00000000"

diff --git a/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/tb/fpga_core/Makefile b/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/tb/fpga_core/Makefile
@@ -174,7 +174,7 @@ export PARAM_RX_CHECKSUM_ENABLE := 1
 export PARAM_LFC_ENABLE := 1
 export PARAM_PFC_ENABLE := $(PARAM_LFC_ENABLE)
 export PARAM_TX_FIFO_DEPTH := 32768
-export PARAM_RX_FIFO_DEPTH := 32768
+export PARAM_RX_FIFO_DEPTH := 65536
 export PARAM_MAX_TX_SIZE := 9214
 export PARAM_MAX_RX_SIZE := 9214
 export PARAM_TX_RAM_SIZE := 32768

diff --git a/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/tb/fpga_core/test_fpga_core.py
@@ -792,7 +792,7 @@ def test_fpga_core(request):
     parameters['LFC_ENABLE'] = 1
     parameters['PFC_ENABLE'] = parameters['LFC_ENABLE']
     parameters['TX_FIFO_DEPTH'] = 32768
-    parameters['RX_FIFO_DEPTH'] = 32768
+    parameters['RX_FIFO_DEPTH'] = 65536
     parameters['MAX_TX_SIZE'] = 9214
     parameters['MAX_RX_SIZE'] = 9214
     parameters['TX_RAM_SIZE'] = 32768

diff --git a/fpga/mqnic/IA_420F/fpga_100g/fpga_25g/config.tcl b/fpga/mqnic/IA_420F/fpga_100g/fpga_25g/config.tcl
@@ -111,7 +111,7 @@ dict set params RX_FIFO_DEPTH "65536"
 dict set params MAX_TX_SIZE "9214"
 dict set params MAX_RX_SIZE "9214"
 dict set params TX_RAM_SIZE "32768"
-dict set params RX_RAM_SIZE "32768"
+dict set params RX_RAM_SIZE "131072"
 
 # Application block configuration
 dict set params APP_ID "32'h00000000"

diff --git a/fpga/mqnic/KR260/fpga/tb/fpga_core/Makefile b/fpga/mqnic/KR260/fpga/tb/fpga_core/Makefile
@@ -158,7 +158,7 @@ export PARAM_RX_CHECKSUM_ENABLE := 1
 export PARAM_LFC_ENABLE := 1
 export PARAM_PFC_ENABLE := $(PARAM_LFC_ENABLE)
 export PARAM_TX_FIFO_DEPTH := 32768
-export PARAM_RX_FIFO_DEPTH := 32768
+export PARAM_RX_FIFO_DEPTH := 65536
 export PARAM_MAX_TX_SIZE := 9214
 export PARAM_MAX_RX_SIZE := 9214
 export PARAM_TX_RAM_SIZE := 32768

diff --git a/fpga/mqnic/KR260/fpga/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/KR260/fpga/tb/fpga_core/test_fpga_core.py
@@ -561,7 +561,7 @@ def test_fpga_core(request):
     parameters['LFC_ENABLE'] = 1
     parameters['PFC_ENABLE'] = parameters['LFC_ENABLE']
     parameters['TX_FIFO_DEPTH'] = 32768
-    parameters['RX_FIFO_DEPTH'] = 32768
+    parameters['RX_FIFO_DEPTH'] = 65536
     parameters['MAX_TX_SIZE'] = 9214
     parameters['MAX_RX_SIZE'] = 9214
     parameters['TX_RAM_SIZE'] = 32768

diff --git a/fpga/mqnic/NetFPGA_SUME/fpga/fpga/config.tcl b/fpga/mqnic/NetFPGA_SUME/fpga/fpga/config.tcl
@@ -111,7 +111,7 @@ dict set params RX_FIFO_DEPTH "65536"
 dict set params MAX_TX_SIZE "9214"
 dict set params MAX_RX_SIZE "9214"
 dict set params TX_RAM_SIZE "32768"
-dict set params RX_RAM_SIZE "32768"
+dict set params RX_RAM_SIZE "65536"
 
 # Application block configuration
 dict set params APP_ID "32'h00000000"

diff --git a/fpga/mqnic/NetFPGA_SUME/fpga/fpga_app_dma_bench/config.tcl b/fpga/mqnic/NetFPGA_SUME/fpga/fpga_app_dma_bench/config.tcl
@@ -111,7 +111,7 @@ dict set params RX_FIFO_DEPTH "65536"
 dict set params MAX_TX_SIZE "9214"
 dict set params MAX_RX_SIZE "9214"
 dict set params TX_RAM_SIZE "32768"
-dict set params RX_RAM_SIZE "32768"
+dict set params RX_RAM_SIZE "65536"
 
 # Application block configuration
 dict set params APP_ID "32'h12348001"

diff --git a/fpga/mqnic/NetFPGA_SUME/fpga/tb/fpga_core/Makefile b/fpga/mqnic/NetFPGA_SUME/fpga/tb/fpga_core/Makefile
@@ -172,11 +172,11 @@ export PARAM_RX_CHECKSUM_ENABLE := 1
 export PARAM_LFC_ENABLE := 1
 export PARAM_PFC_ENABLE := $(PARAM_LFC_ENABLE)
 export PARAM_TX_FIFO_DEPTH := 32768
-export PARAM_RX_FIFO_DEPTH := 32768
+export PARAM_RX_FIFO_DEPTH := 65536
 export PARAM_MAX_TX_SIZE := 9214
 export PARAM_MAX_RX_SIZE := 9214
 export PARAM_TX_RAM_SIZE := 32768
-export PARAM_RX_RAM_SIZE := 32768
+export PARAM_RX_RAM_SIZE := 65536
 
 # Application block configuration
 export PARAM_APP_ID := $(shell echo $$((0x00000000)) )

diff --git a/fpga/mqnic/NetFPGA_SUME/fpga/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/NetFPGA_SUME/fpga/tb/fpga_core/test_fpga_core.py
@@ -782,11 +782,11 @@ def test_fpga_core(request):
     parameters['LFC_ENABLE'] = 1
     parameters['PFC_ENABLE'] = parameters['LFC_ENABLE']
     parameters['TX_FIFO_DEPTH'] = 32768
-    parameters['RX_FIFO_DEPTH'] = 32768
+    parameters['RX_FIFO_DEPTH'] = 65536
     parameters['MAX_TX_SIZE'] = 9214
     parameters['MAX_RX_SIZE'] = 9214
     parameters['TX_RAM_SIZE'] = 32768
-    parameters['RX_RAM_SIZE'] = 32768
+    parameters['RX_RAM_SIZE'] = 65536
 
     # Application block configuration
     parameters['APP_ID'] = 0x00000000

diff --git a/fpga/mqnic/Nexus_K3P_Q/fpga_25g/tb/fpga_core/Makefile b/fpga/mqnic/Nexus_K3P_Q/fpga_25g/tb/fpga_core/Makefile
@@ -174,7 +174,7 @@ export PARAM_RX_CHECKSUM_ENABLE := 1
 export PARAM_LFC_ENABLE := 1
 export PARAM_PFC_ENABLE := $(PARAM_LFC_ENABLE)
 export PARAM_TX_FIFO_DEPTH := 32768
-export PARAM_RX_FIFO_DEPTH := 32768
+export PARAM_RX_FIFO_DEPTH := 65536
 export PARAM_MAX_TX_SIZE := 9214
 export PARAM_MAX_RX_SIZE := 9214
 export PARAM_TX_RAM_SIZE := 32768

diff --git a/fpga/mqnic/Nexus_K3P_Q/fpga_25g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/Nexus_K3P_Q/fpga_25g/tb/fpga_core/test_fpga_core.py
@@ -832,7 +832,7 @@ def test_fpga_core(request):
     parameters['LFC_ENABLE'] = 1
     parameters['PFC_ENABLE'] = parameters['LFC_ENABLE']
     parameters['TX_FIFO_DEPTH'] = 32768
-    parameters['RX_FIFO_DEPTH'] = 32768
+    parameters['RX_FIFO_DEPTH'] = 65536
     parameters['MAX_TX_SIZE'] = 9214
     parameters['MAX_RX_SIZE'] = 9214
     parameters['TX_RAM_SIZE'] = 32768

diff --git a/fpga/mqnic/Nexus_K3P_S/fpga_25g/tb/fpga_core/Makefile b/fpga/mqnic/Nexus_K3P_S/fpga_25g/tb/fpga_core/Makefile
@@ -175,7 +175,7 @@ export PARAM_RX_CHECKSUM_ENABLE := 1
 export PARAM_LFC_ENABLE := 1
 export PARAM_PFC_ENABLE := $(PARAM_LFC_ENABLE)
 export PARAM_TX_FIFO_DEPTH := 32768
-export PARAM_RX_FIFO_DEPTH := 32768
+export PARAM_RX_FIFO_DEPTH := 65536
 export PARAM_MAX_TX_SIZE := 9214
 export PARAM_MAX_RX_SIZE := 9214
 export PARAM_TX_RAM_SIZE := 32768

diff --git a/fpga/mqnic/Nexus_K3P_S/fpga_25g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/Nexus_K3P_S/fpga_25g/tb/fpga_core/test_fpga_core.py
@@ -825,7 +825,7 @@ def test_fpga_core(request):
     parameters['LFC_ENABLE'] = 1
     parameters['PFC_ENABLE'] = parameters['LFC_ENABLE']
     parameters['TX_FIFO_DEPTH'] = 32768
-    parameters['RX_FIFO_DEPTH'] = 32768
+    parameters['RX_FIFO_DEPTH'] = 65536
     parameters['MAX_TX_SIZE'] = 9214
     parameters['MAX_RX_SIZE'] = 9214
     parameters['TX_RAM_SIZE'] = 32768

diff --git a/fpga/mqnic/VCU108/fpga_25g/fpga/config.tcl b/fpga/mqnic/VCU108/fpga_25g/fpga/config.tcl
@@ -124,7 +124,7 @@ dict set params RX_FIFO_DEPTH "65536"
 dict set params MAX_TX_SIZE "9214"
 dict set params MAX_RX_SIZE "9214"
 dict set params TX_RAM_SIZE "32768"
-dict set params RX_RAM_SIZE "32768"
+dict set params RX_RAM_SIZE "131072"
 
 # RAM configuration
 dict set params DDR_CH "2"

diff --git a/fpga/mqnic/VCU108/fpga_25g/tb/fpga_core/Makefile b/fpga/mqnic/VCU108/fpga_25g/tb/fpga_core/Makefile
@@ -174,11 +174,11 @@ export PARAM_RX_CHECKSUM_ENABLE := 1
 export PARAM_LFC_ENABLE := 1
 export PARAM_PFC_ENABLE := $(PARAM_LFC_ENABLE)
 export PARAM_TX_FIFO_DEPTH := 32768
-export PARAM_RX_FIFO_DEPTH := 32768
+export PARAM_RX_FIFO_DEPTH := 65536
 export PARAM_MAX_TX_SIZE := 9214
 export PARAM_MAX_RX_SIZE := 9214
 export PARAM_TX_RAM_SIZE := 32768
-export PARAM_RX_RAM_SIZE := 32768
+export PARAM_RX_RAM_SIZE := 131072
 
 # Application block configuration
 export PARAM_APP_ID := $(shell echo $$((0x00000000)) )

diff --git a/fpga/mqnic/VCU108/fpga_25g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/VCU108/fpga_25g/tb/fpga_core/test_fpga_core.py
@@ -790,11 +790,11 @@ def test_fpga_core(request):
     parameters['LFC_ENABLE'] = 1
     parameters['PFC_ENABLE'] = parameters['LFC_ENABLE']
     parameters['TX_FIFO_DEPTH'] = 32768
-    parameters['RX_FIFO_DEPTH'] = 32768
+    parameters['RX_FIFO_DEPTH'] = 65536
     parameters['MAX_TX_SIZE'] = 9214
     parameters['MAX_RX_SIZE'] = 9214
     parameters['TX_RAM_SIZE'] = 32768
-    parameters['RX_RAM_SIZE'] = 32768
+    parameters['RX_RAM_SIZE'] = 131072
 
     # Application block configuration
     parameters['APP_ID'] = 0x00000000

diff --git a/fpga/mqnic/VCU118/fpga_25g/tb/fpga_core/Makefile b/fpga/mqnic/VCU118/fpga_25g/tb/fpga_core/Makefile
@@ -174,7 +174,7 @@ export PARAM_RX_CHECKSUM_ENABLE := 1
 export PARAM_LFC_ENABLE := 1
 export PARAM_PFC_ENABLE := $(PARAM_LFC_ENABLE)
 export PARAM_TX_FIFO_DEPTH := 32768
-export PARAM_RX_FIFO_DEPTH := 32768
+export PARAM_RX_FIFO_DEPTH := 65536
 export PARAM_MAX_TX_SIZE := 9214
 export PARAM_MAX_RX_SIZE := 9214
 export PARAM_TX_RAM_SIZE := 32768

diff --git a/fpga/mqnic/VCU118/fpga_25g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/VCU118/fpga_25g/tb/fpga_core/test_fpga_core.py
@@ -836,7 +836,7 @@ def test_fpga_core(request):
     parameters['LFC_ENABLE'] = 1
     parameters['PFC_ENABLE'] = parameters['LFC_ENABLE']
     parameters['TX_FIFO_DEPTH'] = 32768
-    parameters['RX_FIFO_DEPTH'] = 32768
+    parameters['RX_FIFO_DEPTH'] = 65536
     parameters['MAX_TX_SIZE'] = 9214
     parameters['MAX_RX_SIZE'] = 9214
     parameters['TX_RAM_SIZE'] = 32768

diff --git a/fpga/mqnic/XUPP3R/fpga_25g/fpga_XUSP3S/config.tcl b/fpga/mqnic/XUPP3R/fpga_25g/fpga_XUSP3S/config.tcl
@@ -124,7 +124,7 @@ dict set params RX_FIFO_DEPTH "65536"
 dict set params MAX_TX_SIZE "9214"
 dict set params MAX_RX_SIZE "9214"
 dict set params TX_RAM_SIZE "32768"
-dict set params RX_RAM_SIZE "32768"
+dict set params RX_RAM_SIZE "131072"
 
 # RAM configuration
 dict set params DDR_CH "4"

diff --git a/fpga/mqnic/XUPP3R/fpga_25g/tb/fpga_core/Makefile b/fpga/mqnic/XUPP3R/fpga_25g/tb/fpga_core/Makefile
@@ -174,7 +174,7 @@ export PARAM_RX_CHECKSUM_ENABLE := 1
 export PARAM_LFC_ENABLE := 1
 export PARAM_PFC_ENABLE := $(PARAM_LFC_ENABLE)
 export PARAM_TX_FIFO_DEPTH := 32768
-export PARAM_RX_FIFO_DEPTH := 32768
+export PARAM_RX_FIFO_DEPTH := 65536
 export PARAM_MAX_TX_SIZE := 9214
 export PARAM_MAX_RX_SIZE := 9214
 export PARAM_TX_RAM_SIZE := 32768

diff --git a/fpga/mqnic/XUPP3R/fpga_25g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/XUPP3R/fpga_25g/tb/fpga_core/test_fpga_core.py
@@ -833,7 +833,7 @@ def test_fpga_core(request):
     parameters['LFC_ENABLE'] = 1
     parameters['PFC_ENABLE'] = parameters['LFC_ENABLE']
     parameters['TX_FIFO_DEPTH'] = 32768
-    parameters['RX_FIFO_DEPTH'] = 32768
+    parameters['RX_FIFO_DEPTH'] = 65536
     parameters['MAX_TX_SIZE'] = 9214
     parameters['MAX_RX_SIZE'] = 9214
     parameters['TX_RAM_SIZE'] = 32768

diff --git a/fpga/mqnic/ZCU102/fpga/tb/fpga_core/Makefile b/fpga/mqnic/ZCU102/fpga/tb/fpga_core/Makefile
@@ -158,7 +158,7 @@ export PARAM_RX_CHECKSUM_ENABLE := 1
 export PARAM_LFC_ENABLE := 1
 export PARAM_PFC_ENABLE := $(PARAM_LFC_ENABLE)
 export PARAM_TX_FIFO_DEPTH := 32768
-export PARAM_RX_FIFO_DEPTH := 32768
+export PARAM_RX_FIFO_DEPTH := 65536
 export PARAM_MAX_TX_SIZE := 9214
 export PARAM_MAX_RX_SIZE := 9214
 export PARAM_TX_RAM_SIZE := 32768

diff --git a/fpga/mqnic/ZCU102/fpga/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/ZCU102/fpga/tb/fpga_core/test_fpga_core.py
@@ -582,7 +582,7 @@ def test_fpga_core(request):
     parameters['LFC_ENABLE'] = 1
     parameters['PFC_ENABLE'] = parameters['LFC_ENABLE']
     parameters['TX_FIFO_DEPTH'] = 32768
-    parameters['RX_FIFO_DEPTH'] = 32768
+    parameters['RX_FIFO_DEPTH'] = 65536
     parameters['MAX_TX_SIZE'] = 9214
     parameters['MAX_RX_SIZE'] = 9214
     parameters['TX_RAM_SIZE'] = 32768

diff --git a/fpga/mqnic/ZCU102/fpga/tb/fpga_core_app_custom_port_demo/Makefile b/fpga/mqnic/ZCU102/fpga/tb/fpga_core_app_custom_port_demo/Makefile
@@ -160,7 +160,7 @@ export PARAM_RX_CHECKSUM_ENABLE := 1
 export PARAM_LFC_ENABLE := 1
 export PARAM_PFC_ENABLE := $(PARAM_LFC_ENABLE)
 export PARAM_TX_FIFO_DEPTH := 32768
-export PARAM_RX_FIFO_DEPTH := 32768
+export PARAM_RX_FIFO_DEPTH := 65536
 export PARAM_MAX_TX_SIZE := 9214
 export PARAM_MAX_RX_SIZE := 9214
 export PARAM_TX_RAM_SIZE := 32768

diff --git a/fpga/mqnic/ZCU102/fpga/tb/fpga_core_app_custom_port_demo/test_fpga_core.py b/fpga/mqnic/ZCU102/fpga/tb/fpga_core_app_custom_port_demo/test_fpga_core.py
@@ -588,7 +588,7 @@ def test_fpga_core(request):
     parameters['LFC_ENABLE'] = 1
     parameters['PFC_ENABLE'] = parameters['LFC_ENABLE']
     parameters['TX_FIFO_DEPTH'] = 32768
-    parameters['RX_FIFO_DEPTH'] = 32768
+    parameters['RX_FIFO_DEPTH'] = 65536
     parameters['MAX_TX_SIZE'] = 9214
     parameters['MAX_RX_SIZE'] = 9214
     parameters['TX_RAM_SIZE'] = 32768