TIA

OA/bag3_analog/buf_cmos_cell/schematic/master.tag

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OA/bag3_analog/buf_cmos_cell/symbol/master.tag

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OA/bag3_analog/tia/schematic/master.tag

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OA/bag3_analog/tia/symbol/master.tag

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OA/bag3_analog/tia_res/schematic/master.tag

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OA/bag3_analog/tia_res/symbol/master.tag

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OA/bag3_analog/tia_term/schematic/master.tag

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OA/bag3_analog/tia_term/symbol/master.tag

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src/bag3_analog/schematic/buf_cmos_cell.py

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+# BSD 3-Clause License
+#
+# Copyright (c) 2018, Regents of the University of California
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are met:
+#
+# * Redistributions of source code must retain the above copyright notice, this
+#   list of conditions and the following disclaimer.
+#
+# * Redistributions in binary form must reproduce the above copyright notice,
+#   this list of conditions and the following disclaimer in the documentation
+#   and/or other materials provided with the distribution.
+#
+# * Neither the name of the copyright holder nor the names of its
+#   contributors may be used to endorse or promote products derived from
+#   this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+# DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+# FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+# DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+# SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+# CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+# OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+# -*- coding: utf-8 -*-
+
+from typing import Mapping, Any, List, Tuple
+
+import pkg_resources
+from pathlib import Path
+
+from bag.design.module import Module
+from bag.design.database import ModuleDB
+from bag.util.immutable import Param
+
+
+# noinspection PyPep8Naming
+class bag3_analog__buf_cmos_cell(Module):
+    """Module for library bag3_analog cell buf_cmos_cell.
+
+    Fill in high level description here.
+    """
+
+    yaml_file = pkg_resources.resource_filename(__name__,
+                                                str(Path('netlist_info',
+                                                         'buf_cmos_cell.yaml')))
+
+    def __init__(self, database: ModuleDB, params: Param, **kwargs: Any) -> None:
+        Module.__init__(self, self.yaml_file, database, params, **kwargs)
+
+    @classmethod
+    def get_params_info(cls) -> Mapping[str, str]:
+        """Returns a dictionary from parameter names to descriptions.
+
+        Returns
+        -------
+        param_info : Optional[Mapping[str, str]]
+            dictionary from parameter names to descriptions.
+        """
+        return dict(
+            lch='channel length, in meters.',
+            w_n='pmos/nmos width, in meters/number of fins.',
+            seg_n='nmos number of fingers.',
+            w_p='pmos/nmos width, in meters/number of fins.',
+            seg_p='nmos number of fingers.',
+            th_p='pmos transistor threshold',
+            th_n='nmos transistor threshold',
+            dum_info='dummy information',
+        )
+
+    @classmethod
+    def get_default_param_values(cls) -> Mapping[str, Any]:
+        return dict(
+            dum_info=None,
+        )
+
+    def design(self, lch: int, w_n: int, w_p: int, seg_n: int, seg_p: int, th_p: str, th_n: str,
+               dum_info: List[Tuple]) -> None:
+        self.instances['XN0'].design(w=w_n, l=lch, nf=seg_n, intent=th_n)
+        self.instances['XN1'].design(w=w_n, l=lch, nf=seg_n, intent=th_n)
+        self.instances['XP0'].design(w=w_p, l=lch, nf=seg_p, intent=th_p)
+        self.instances['XP1'].design(w=w_p, l=lch, nf=seg_p, intent=th_p)
+
+        # dummy
+        self.design_dummy_transistors(dum_info, 'XDUM', 'VDDA', 'VSS')