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Changed processor clock to be independent of the USB clock. Set proce…
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…ssor clock to be 80MHz. The UART will now be at 115200*80/60=153600 baud
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@vr2045
vr2045 committed Mar 18, 2024
1 parent fb53a80 commit 980bce5
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Showing 18 changed files with 4,116 additions and 55 deletions.
6 changes: 6 additions & 0 deletions .gitmodules
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Expand Up @@ -34,3 +34,9 @@
[submodule "ip/wb2axip"]
path = RTL/ip/wb2axip
url = https://github.com/ZipCPU/wb2axip.git
[submodule "RTL/ip/wb_bfm"]
path = RTL/ip/wb_bfm
url = https://github.com/olofk/wb_bfm.git
[submodule "RTL/ip/stream_utils"]
path = RTL/ip/stream_utils
url = https://github.com/olofk/stream_utils.git
2 changes: 2 additions & 0 deletions Firmware/example_i2c_init/Makefile
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Expand Up @@ -26,6 +26,8 @@ crt0.o: $(CPU_DIRECTORY)/crt0.S

%.bin: %.elf
$(OBJCOPY) -O binary $< $@
mkdir -p ../../RTL/sim
od -v -An -tx1 firmware.bin > ../../RTL/sim/firmware.hex

clean:
$(RM) *.o *.d *.elf *.bin *.map
6 changes: 3 additions & 3 deletions RTL/ip/main_pll/constraints/main_pll.ldc
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Expand Up @@ -34,10 +34,10 @@ set CLKOP_TRIM "0b0000"
set CLKOS_EN 1
set CLKOS_BYPASS 0
set ENCLKOS_EN 0
set CLKOS_FREQ_ACTUAL 100.000000
set CLKOS_FREQ_ACTUAL 80.000000
set CLKOS_PHASE_ACTUAL 0.000000
set DIVOS_ACTUAL_STR "11"
set DELB "11"
set DIVOS_ACTUAL_STR "14"
set DELB "14"
set PHIB "0"
set TRIM_EN_S 0
set CLKOS_TRIM_MODE "Falling"
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2 changes: 1 addition & 1 deletion RTL/ip/main_pll/main_pll.cfg
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Expand Up @@ -4,7 +4,7 @@
"gui_refclk_freq": 24.0,
"gui_clk_op_freq": 60.0,
"gui_clk_os_en": true,
"gui_clk_os_freq": 100.0,
"gui_clk_os_freq": 80.0,
"gui_clk_os_tol": 10.0,
"gui_clk_s2_en": true,
"gui_clk_s2_freq": 100.0,
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22 changes: 11 additions & 11 deletions RTL/ip/main_pll/main_pll.ipx
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@@ -1,16 +1,16 @@
<?xml version="1.0" ?>
<RadiantModule architecture="LIFCL" date="2024 02 14 16:06:43" device="LIFCL-33U" gen_platform="Radiant" generator="ipgen" library="module" module="pll" name="main_pll" package="FCCSP104" source_format="Verilog" speed="7_High-Performance_1.0V" vendor="latticesemi.com" version="1.8.0">
<RadiantModule architecture="LIFCL" date="2024 03 17 12:20:48" device="LIFCL-33U" gen_platform="Radiant" generator="ipgen" library="module" module="pll" name="main_pll" package="FCCSP104" source_format="Verilog" speed="7_High-Performance_1.0V" vendor="latticesemi.com" version="1.8.0">
<Package>
<File modified="2024 02 14 16:06:43" name="rtl/main_pll_bb.v" type="black_box_verilog"/>
<File modified="2024 02 14 16:06:43" name="main_pll.cfg" type="cfg"/>
<File modified="2024 02 14 16:06:43" name="misc/main_pll_tmpl.v" type="template_verilog"/>
<File modified="2024 02 14 16:06:43" name="misc/main_pll_tmpl.vhd" type="template_vhdl"/>
<File modified="2024 02 14 16:06:43" name="rtl/main_pll.v" type="top_level_verilog"/>
<File modified="2024 02 14 16:06:43" name="constraints/main_pll.ldc" type="timing_constraints"/>
<File modified="2024 02 14 16:06:43" name="testbench/dut_params.v" type="dependency_file"/>
<File modified="2024 02 14 16:06:43" name="testbench/dut_inst.v" type="dependency_file"/>
<File modified="2024 02 14 16:06:43" name="component.xml" type="IP-XACT_component"/>
<File modified="2024 02 14 16:06:43" name="design.xml" type="IP-XACT_design"/>
<File modified="2024 03 17 12:20:48" name="rtl/main_pll_bb.v" type="black_box_verilog"/>
<File modified="2024 03 17 12:20:48" name="main_pll.cfg" type="cfg"/>
<File modified="2024 03 17 12:20:48" name="misc/main_pll_tmpl.v" type="template_verilog"/>
<File modified="2024 03 17 12:20:48" name="misc/main_pll_tmpl.vhd" type="template_vhdl"/>
<File modified="2024 03 17 12:20:48" name="rtl/main_pll.v" type="top_level_verilog"/>
<File modified="2024 03 17 12:20:48" name="constraints/main_pll.ldc" type="timing_constraints"/>
<File modified="2024 03 17 12:20:48" name="testbench/dut_params.v" type="dependency_file"/>
<File modified="2024 03 17 12:20:48" name="testbench/dut_inst.v" type="dependency_file"/>
<File modified="2024 03 17 12:20:48" name="component.xml" type="IP-XACT_component"/>
<File modified="2024 03 17 12:20:48" name="design.xml" type="IP-XACT_design"/>
<File modified="2021 05 21 00:57:55" name="testbench/tb_top.v" type="testbench_verilog"/>
</Package>
</RadiantModule>
8 changes: 4 additions & 4 deletions RTL/ip/main_pll/rtl/main_pll.v
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Expand Up @@ -3,7 +3,7 @@
Verilog netlist generated by IPGEN Lattice Radiant Software (64-bit)
2023.2.0.38.1
Soft IP Version: 1.8.0
2024 02 14 16:06:43
2024 03 17 12:20:48
*******************************************************************************/
/*******************************************************************************
Wrapper Module generated per user settings.
Expand Down Expand Up @@ -57,10 +57,10 @@ module main_pll (clki_i,
.CLKOS_EN(1),
.CLKOS_BYPASS(0),
.ENCLKOS_EN(0),
.CLKOS_FREQ_ACTUAL(100.0),
.CLKOS_FREQ_ACTUAL(80.0),
.CLKOS_PHASE_ACTUAL(0.0),
.DIVOS_ACTUAL_STR("11"),
.DELB("11"),
.DIVOS_ACTUAL_STR("14"),
.DELB("14"),
.PHIB("0"),
.TRIM_EN_S(0),
.CLKOS_TRIM_MODE("Falling"),
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2 changes: 1 addition & 1 deletion RTL/ip/main_pll/rtl/main_pll_bb.v
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Expand Up @@ -2,7 +2,7 @@
Verilog netlist generated by IPGEN Lattice Radiant Software (64-bit)
2023.2.0.38.1
Soft IP Version: 1.8.0
2024 02 14 16:06:43
2024 03 17 12:20:48
*******************************************************************************/
/*******************************************************************************
Wrapper Module generated per user settings.
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6 changes: 3 additions & 3 deletions RTL/ip/main_pll/testbench/dut_params.v
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Expand Up @@ -29,10 +29,10 @@ localparam CLKOP_TRIM = "0b0000";
localparam CLKOS_EN = 1;
localparam CLKOS_BYPASS = 0;
localparam ENCLKOS_EN = 0;
localparam CLKOS_FREQ_ACTUAL = 100.000000;
localparam CLKOS_FREQ_ACTUAL = 80.000000;
localparam CLKOS_PHASE_ACTUAL = 0.000000;
localparam DIVOS_ACTUAL_STR = "11";
localparam DELB = "11";
localparam DIVOS_ACTUAL_STR = "14";
localparam DELB = "14";
localparam PHIB = "0";
localparam TRIM_EN_S = 0;
localparam CLKOS_TRIM_MODE = "Falling";
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1 change: 1 addition & 0 deletions RTL/ip/stream_utils
Submodule stream_utils added at 5f54bc
1 change: 1 addition & 0 deletions RTL/ip/wb_bfm
Submodule wb_bfm added at c433bb
6 changes: 3 additions & 3 deletions RTL/sim/Makefile
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Expand Up @@ -6,15 +6,15 @@ WORKDIR = work

RTL = ../src
TB = ../tb
RISCV = ../litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog
#RISCV = ../litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog
COMMON = ../common
COMMON_IP = $(COMMON)/ip
COMMON_IP = ../ip
IP = ../ip
LITEX = ../litex/build/som/gateware

TOP = fpga_top_lifcl33u_som
SIM_SRCS = $(IP)/wb2axip/rtl/afifo.v $(IP)/wb2axip/rtl/wbxclk.v
SIM_SRCS += $(RISCV)/VexRiscv_Full.v
SIM_SRCS += $(RTL)/VexRiscv.v
SIM_SRCS += $(TB)/tb_$(TOP).sv


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