Clock dividers

Clock dividers to reduce clock frequency by the powers of two. Two types of modules implemented:

• Static (Fixed): These can provide only one fixed output frequency. They are named clk_divN, where N is the division power. (e.g. clk_div2 provides ¼ of the input frequency)

• Dynamic (Variable): Output frequency of these dividers can be controlled by rate_cntrl. Higher rate_cntrl value give lower output frequency. They are named dclk_divN_M. Where M is the step size and N is the maximum division power over step size. (e.g. dclk_div2_2 can generate two frequencies controlled by single bit rate_cntrl signal, 1/4 and 1/16 of the input frequency)

Some of the modules simulated with Icarus Verilog.