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Mips update #4621

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Mips update #4621

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e4afbea
Remove mips gnu, rename mips_cs to mips and update the code
wargio Sep 7, 2024
a72be4f
Update capstone-next wrap
wargio Sep 8, 2024
163d3f4
Add support to various mips cpus and features
wargio Sep 7, 2024
05f8840
Split esil from analysis_mips.c
wargio Sep 8, 2024
658a0ce
Fix compilation and tests
wargio Sep 11, 2024
925368d
Fix systemz with capstone 6
wargio Sep 26, 2024
db6f9f8
Handle ldr case without base register.
Rot127 Sep 28, 2024
7c44218
Fix ARM64 & ARM32 compilation with latest CS6 commit
wargio Sep 27, 2024
730556d
Fix asm tests
wargio Sep 30, 2024
4ba4538
Small cleanup and upgrade of capstone
wargio Sep 30, 2024
f3a8f33
Fix luac since it using cpu but doesn't define them
wargio Sep 30, 2024
335f7b5
Add sysz cpus even if they are not used yet
wargio Sep 30, 2024
bcfe896
Fix tests
wargio Sep 30, 2024
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7 changes: 2 additions & 5 deletions librz/arch/isa/arm/aarch64_meta_macros.h
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Original file line number Diff line number Diff line change
Expand Up @@ -4,8 +4,6 @@
#ifndef AARCH64_META_MACROS_H
#define AARCH64_META_MACROS_H

#ifdef USE_SYS_CAPSTONE

/// Macro for meta programming.
/// Meant for projects using Capstone and need to support multiple
/// versions of it.
Expand All @@ -14,7 +12,7 @@
#if CS_NEXT_VERSION < 6
#define CS_AARCH64(x) ARM64##x
#else
#define CS_AARCH64(x) AArch64##x
#define CS_AARCH64(x) AARCH64##x
#endif

#if CS_NEXT_VERSION < 6
Expand All @@ -32,7 +30,7 @@
#if CS_NEXT_VERSION < 6
#define CS_AARCH64_VL_(x) ARM64_VAS_##x
#else
#define CS_AARCH64_VL_(x) AArch64Layout_VL_##x
#define CS_AARCH64_VL_(x) AARCH64LAYOUT_VL_##x
#endif

#if CS_NEXT_VERSION < 6
Expand Down Expand Up @@ -65,5 +63,4 @@
#define CS_aarch64_vas() AArch64Layout_VectorLayout
#endif

#endif // USE_SYS_CAPSTONE
#endif // AARCH64_META_MACROS_H
5 changes: 2 additions & 3 deletions librz/arch/isa/arm/arm_accessors32.h
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Expand Up @@ -27,14 +27,13 @@
#define ISMEM(x) (insn->detail->arm.operands[x].type == ARM_OP_MEM)
#define ISFPIMM(x) (insn->detail->arm.operands[x].type == ARM_OP_FP)

#define LSHIFT(x) insn->detail->arm.operands[x].mem.lshift
#define LSHIFT(x) insn->detail->arm.operands[x].shift.value
#define LSHIFT2(x) insn->detail->arm.operands[x].shift.value // Dangerous, returns value even if isn't LSL
#define OPCOUNT() insn->detail->arm.op_count
#define ISSHIFTED(x) (insn->detail->arm.operands[x].shift.type != ARM_SFT_INVALID && insn->detail->arm.operands[x].shift.value != 0)
#define SHIFTTYPE(x) insn->detail->arm.operands[x].shift.type
#define SHIFTTYPEREG(x) (SHIFTTYPE(x) == ARM_SFT_ASR_REG || SHIFTTYPE(x) == ARM_SFT_LSL_REG || \
SHIFTTYPE(x) == ARM_SFT_LSR_REG || SHIFTTYPE(x) == ARM_SFT_ROR_REG || \
SHIFTTYPE(x) == ARM_SFT_RRX_REG)
SHIFTTYPE(x) == ARM_SFT_LSR_REG || SHIFTTYPE(x) == ARM_SFT_ROR_REG)
#define SHIFTVALUE(x) insn->detail->arm.operands[x].shift.value

#if CS_NEXT_VERSION >= 6
Expand Down
2 changes: 2 additions & 0 deletions librz/arch/isa/arm/arm_esil32.c
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Original file line number Diff line number Diff line change
Expand Up @@ -34,7 +34,9 @@ static const char *decode_shift(arm_shifter shift) {
case ARM_SFT_ROR:
case ARM_SFT_RRX:
case ARM_SFT_ROR_REG:
#if CS_NEXT_VERSION < 6
case ARM_SFT_RRX_REG:
#endif
return E_OP_RR;

default:
Expand Down
43 changes: 24 additions & 19 deletions librz/arch/isa/arm/arm_esil64.c
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Original file line number Diff line number Diff line change
Expand Up @@ -294,12 +294,12 @@ static void bfm(RzAnalysisOp *op, csh *handle, cs_insn *insn) {
switch (insn->alias_id) {
default:
return;
case AArch64_INS_ALIAS_BFI: // bfi w8, w8, 2, 1
case AARCH64_INS_ALIAS_BFI: // bfi w8, w8, 2, 1
width += 1;
// TODO Mod depends on (sf && N) bits
lsb = -lsb % 32;
break;
case AArch64_INS_ALIAS_BFXIL:
case AARCH64_INS_ALIAS_BFXIL:
width = width - lsb + 1;
break;
}
Expand All @@ -314,25 +314,25 @@ static void bfm(RzAnalysisOp *op, csh *handle, cs_insn *insn) {
static void subfm(RzAnalysisOp *op, csh *handle, cs_insn *insn) {
ut64 lsb = IMM64(2);
ut64 width = IMM64(3);
if (insn->alias_id == AArch64_INS_ALIAS_SBFIZ) {
if (insn->alias_id == AARCH64_INS_ALIAS_SBFIZ) {
width += 1;
lsb = -lsb % 64;
rz_strbuf_appendf(&op->esil, "%" PFMT64d ",%" PFMT64d ",%s,%" PFMT64u ",&,~,<<,%s,=",
lsb, IMM64(3), REG64(1), rz_num_bitmask((ut8)width), REG64(0));
} else if (insn->alias_id == AArch64_INS_ALIAS_UBFIZ) {
} else if (insn->alias_id == AARCH64_INS_ALIAS_UBFIZ) {
width += 1;
lsb = -lsb % 64;
rz_strbuf_appendf(&op->esil, "%" PFMT64d ",%s,%" PFMT64u ",&,<<,%s,=",
lsb, REG64(1), rz_num_bitmask((ut8)width), REG64(0));
} else if (insn->alias_id == AArch64_INS_ALIAS_SBFX) {
} else if (insn->alias_id == AARCH64_INS_ALIAS_SBFX) {
width = width - lsb + 1;
rz_strbuf_appendf(&op->esil, "%" PFMT64d ",%" PFMT64d ",%s,%" PFMT64d ",%" PFMT64u ",<<,&,>>,~,%s,=",
IMM64(3), IMM64(2), REG64(1), IMM64(2), rz_num_bitmask((ut8)IMM64(3)), REG64(0));
} else if (insn->alias_id == AArch64_INS_ALIAS_UBFX) {
} else if (insn->alias_id == AARCH64_INS_ALIAS_UBFX) {
width = width - lsb + 1;
rz_strbuf_appendf(&op->esil, "%" PFMT64d ",%s,%" PFMT64d ",%" PFMT64u ",<<,&,>>,%s,=",
lsb, REG64(1), lsb, rz_num_bitmask((ut8)width), REG64(0));
} else if (insn->alias_id == AArch64_INS_ALIAS_LSL) {
} else if (insn->alias_id == AARCH64_INS_ALIAS_LSL) {
// imms != 0x1f => mod 32
// imms != 0x3f => mod 64
ut32 m = IMM64(3) != 0x1f ? 32 : 64;
Expand All @@ -352,7 +352,7 @@ static void subfm(RzAnalysisOp *op, csh *handle, cs_insn *insn) {
ut64 i2 = IMM64(2) % m;
rz_strbuf_setf(&op->esil, "%" PFMT64d ",%s,<<,%s,=", i2 % (ut64)size, r1, r0);
}
} else if (insn->alias_id == AArch64_INS_ALIAS_LSR) {
} else if (insn->alias_id == AARCH64_INS_ALIAS_LSR) {
const char *r0 = REG64(0);
const char *r1 = REG64(1);
const int size = REGSIZE64(0) * 8;
Expand All @@ -369,7 +369,7 @@ static void subfm(RzAnalysisOp *op, csh *handle, cs_insn *insn) {
ut64 i2 = IMM64(2);
rz_strbuf_setf(&op->esil, "%" PFMT64d ",%s,>>,%s,=", i2 % (ut64)size, r1, r0);
}
} else if (insn->alias_id == AArch64_INS_ALIAS_ASR) {
} else if (insn->alias_id == AARCH64_INS_ALIAS_ASR) {
const char *r0 = REG64(0);
const char *r1 = REG64(1);
const int size = REGSIZE64(0) * 8;
Expand Down Expand Up @@ -713,8 +713,13 @@ RZ_IPI int rz_arm_cs_analysis_op_64_esil(RzAnalysis *a, RzAnalysisOp *op, ut64 a
rz_strbuf_appendf(&op->esil, "%" PFMT64d ",%s,-",
-(st64)MEMDISP64(1), MEMBASE64(1));
} else {
rz_strbuf_appendf(&op->esil, "%" PFMT64d ",%s,+",
MEMDISP64(1), MEMBASE64(1));
if (insn->detail->CS_aarch64_.operands[1].mem.base == 0) {
rz_strbuf_appendf(&op->esil, "%" PFMT64d,
MEMDISP64(1));
} else {
rz_strbuf_appendf(&op->esil, "%" PFMT64d ",%s,+",
MEMDISP64(1), MEMBASE64(1));
}
}

rz_strbuf_append(&op->esil, ",DUP,tmp,=");
Expand Down Expand Up @@ -883,9 +888,9 @@ RZ_IPI int rz_arm_cs_analysis_op_64_esil(RzAnalysis *a, RzAnalysisOp *op, ut64 a
break;
}
#if CS_NEXT_VERSION >= 6
case AArch64_INS_SUBS:
if (insn->alias_id != AArch64_INS_ALIAS_CMP &&
insn->alias_id != AArch64_INS_ALIAS_CMN) {
case AARCH64_INS_SUBS:
if (insn->alias_id != AARCH64_INS_ALIAS_CMP &&
insn->alias_id != AARCH64_INS_ALIAS_CMN) {
cmp(op, handle, insn);
break;
}
Expand Down Expand Up @@ -926,13 +931,13 @@ RZ_IPI int rz_arm_cs_analysis_op_64_esil(RzAnalysis *a, RzAnalysisOp *op, ut64 a
rz_strbuf_appendf(&op->esil, "%s,}{,1,%s,+,},%s,=", REG64(1), REG64(2), REG64(0));
postfix = "";
break;
case AArch64_INS_ALIAS_CSET: // cset Wd --> Wd := (cond) ? 1 : 0
case AARCH64_INS_ALIAS_CSET: // cset Wd --> Wd := (cond) ? 1 : 0
rz_strbuf_drain_nofree(&op->esil);
rz_arm64_cs_esil_prefix_cond(op, AArch64CC_getInvertedCondCode(insn->detail->CS_aarch64_.cc));
rz_strbuf_appendf(&op->esil, "1,}{,0,},%s,=", REG64(0));
postfix = "";
break;
case AArch64_INS_ALIAS_CINC: // cinc Wd, Wn --> Wd := (cond) ? (Wn+1) : Wn
case AARCH64_INS_ALIAS_CINC: // cinc Wd, Wn --> Wd := (cond) ? (Wn+1) : Wn
rz_strbuf_drain_nofree(&op->esil);
rz_arm64_cs_esil_prefix_cond(op, AArch64CC_getInvertedCondCode(insn->detail->CS_aarch64_.cc));
rz_strbuf_appendf(&op->esil, "1,%s,+,}{,%s,},%s,=", REG64(1), REG64(1), REG64(0));
Expand Down Expand Up @@ -1322,11 +1327,11 @@ RZ_IPI int rz_arm_cs_analysis_op_64_esil(RzAnalysis *a, RzAnalysisOp *op, ut64 a
}
break;
#else
case AArch64_INS_BFM:
case AARCH64_INS_BFM:
bfm(op, handle, insn);
break;
case AArch64_INS_UBFM:
case AArch64_INS_SBFM:
case AARCH64_INS_UBFM:
case AARCH64_INS_SBFM:
subfm(op, handle, insn);
break;
#endif
Expand Down
4 changes: 4 additions & 0 deletions librz/arch/isa/arm/arm_il32.c
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Original file line number Diff line number Diff line change
Expand Up @@ -348,7 +348,9 @@ static bool is_reg_shift(arm_shifter type) {
case ARM_SFT_LSL_REG:
case ARM_SFT_LSR_REG:
case ARM_SFT_ROR_REG:
#if CS_NEXT_VERSION < 6
case ARM_SFT_RRX_REG:
#endif
return true;
default:
return false;
Expand Down Expand Up @@ -401,7 +403,9 @@ shift(RzILOpBitVector *val, RZ_NULLABLE RzILOpBool **carry_out, arm_shifter type
SHIFTR0(val, dist),
SHIFTL0(DUP(val), NEG(DUP(dist))));
case ARM_SFT_RRX:
#if CS_NEXT_VERSION < 6
case ARM_SFT_RRX_REG:
#endif
if (carry_out) {
*carry_out = LSB(DUP(val));
}
Expand Down
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