Fix build error on loongarch64 (#4558)

rizinorg · Jul 5, 2024 · cbd086a · cbd086a
1 parent 3e258f5
commit cbd086a
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Showing 4 changed files with 303 additions and 241 deletions.
diff --git a/librz/debug/p/native/linux/linux_debug.c b/librz/debug/p/native/linux/linux_debug.c
@@ -83,6 +83,8 @@ char *linux_reg_profile(RzDebug *dbg) {
 	}
 #elif __s390x__
 #include "reg/linux-s390x.h"
+#elif __loongarch64
+#include "reg/linux-loongarch64.h"
 #else
 #error "Unsupported Linux CPU"
 	return NULL;

diff --git a/librz/debug/p/native/linux/linux_debug.h b/librz/debug/p/native/linux/linux_debug.h
@@ -138,6 +138,12 @@ struct powerpc_regs_t {
 // typedef ut64 riscv64_regs_t [65];
 // #define RZ_DEBUG_REG_T riscv64_regs_t
 #define RZ_DEBUG_REG_T struct user_regs_struct
+
+#elif __loongarch64
+#include <sys/ucontext.h>
+#include <asm/ptrace.h>
+#define RZ_DEBUG_REG_T struct user_regs_struct
+
 // #define RZ_DEBUG_REG_T mcontext_t 77 784 in size (coz the fpu regs)
 
 #elif __mips__

diff --git a/librz/debug/p/native/linux/reg/linux-loongarch64.h b/librz/debug/p/native/linux/reg/linux-loongarch64.h
@@ -0,0 +1,52 @@
+// SPDX-FileCopyrightText: 2024 Wenlong Zhang <[email protected]>
+// SPDX-License-Identifier: LGPL-3.0-only
+
+return strdup(
+	"=PC    pc\n"
+	"=SP    sp\n"
+	"=BP    fp\n"
+	"=A0    a0\n"
+	"=A1    a1\n"
+	"=A2    a2\n"
+	"=A3    a3\n"
+	"=A4    a4\n"
+	"=A5    a5\n"
+	"=A6    a6\n"
+	"=A7    a7\n"
+	"gpr    zero    .64     0       0\n"
+	"gpr    ra      .64     8       0\n"
+	"gpr    tp      .64     16      0\n"
+	"gpr    sp      .64     24      0\n"
+	/* args */
+	"gpr    a0      .64     32      0\n"
+	"gpr    a1      .64     40      0\n"
+	"gpr    a2      .64     48      0\n"
+	"gpr    a3      .64     56      0\n"
+	"gpr    a4      .64     64      0\n"
+	"gpr    a5      .64     72      0\n"
+	"gpr    a6      .64     80      0\n"
+	"gpr    a7      .64     88      0\n"
+	/* tmp */
+	"gpr    t0      .64     96      0\n"
+	"gpr    t1      .64     104     0\n"
+	"gpr    t2      .64     112     0\n"
+	"gpr    t3      .64     120     0\n"
+	"gpr    t4      .64     128     0\n"
+	"gpr    t5      .64     136     0\n"
+	"gpr    t6      .64     144     0\n"
+	"gpr    t7      .64     152     0\n"
+	"gpr    t8      .64     160     0\n"
+	/* saved */
+	"gpr    r21     .64     168     0\n" // Non-allocatable
+	/* fp */
+	"gpr    fp      .64     176     0\n"
+	/* static */
+	"gpr    s0      .64     184     0\n"
+	"gpr    s1      .64     192     0\n"
+	"gpr    s2      .64     200     0\n"
+	"gpr    s3      .64     208     0\n"
+	"gpr    s4      .64     216     0\n"
+	"gpr    s5      .64     224     0\n"
+	"gpr    s6      .64     232     0\n"
+	"gpr    s7      .64     240     0\n"
+	"gpr    s8      .64     248     0\n");