test for rotw|round.s|rsil|rsqrt0.s|rsync

rizinorg · Nov 25, 2024 · b012776 · b012776
1 parent 0ec8737
commit b012776
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Showing 2 changed files with 9 additions and 2 deletions.
diff --git a/librz/arch/isa/xtensa/xtensa_il.c b/librz/arch/isa/xtensa/xtensa_il.c
@@ -1093,7 +1093,8 @@ static RzAnalysisLiftedILOp op_rfde(XtensaContext *ctx) {
 	return JMP(ITE(VARG("ndepc"), VARG("depc"), IEPC(1)));
 }
 
-#define PS_EXCM_CLEAR SETG("ps", reg_field_set(&ps_field_tbl, PS_EXCM, VARG("ps"), U32(0)))
+#define PS_field_set(F, V) SETG("ps", reg_field_set(&ps_field_tbl, (F), VARG("ps"), (V)))
+#define PS_EXCM_CLEAR      PS_field_set(PS_EXCM, U32(0))
 
 static RzAnalysisLiftedILOp op_rfe(XtensaContext *ctx) {
 	return SEQ2(
@@ -1138,7 +1139,7 @@ static RzAnalysisLiftedILOp op_round_s(XtensaContext *ctx) {
 
 static RzAnalysisLiftedILOp op_rsil(XtensaContext *ctx) {
 	return SEQ2(SETG(REGN(0), VARG("ps")),
-		SETG("ps.intlevel", U32(IMM(1))));
+		PS_field_set(PS_INTLEVEL, U32(IMM(1))));
 }
 
 // FIXME: statusflags+reciprocal_square_root_approximation

diff --git a/test/db/asm/xtensa b/test/db/asm/xtensa
@@ -221,3 +221,9 @@ d "rfi 2" 103200 0x0 (seq (set ps (var eps2)) (jmp (var epc2)))
 d "rfr a1, f2" 4012fa 0x0 (set a1 (cast 32 false (var f2)))
 d "rfwo" 003400 0x0 (seq (set ps (| (& (var ps) (~ (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false) (bv 32 0x4) false))) (& (<< (bv 32 0x0) (bv 32 0x4) false) (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false) (bv 32 0x4) false)))) (jmp (var epc1)))
 d "rfwu" 003500 0x0 (seq (set ps (| (& (var ps) (~ (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false) (bv 32 0x4) false))) (& (<< (bv 32 0x0) (bv 32 0x4) false) (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false) (bv 32 0x4) false)))) (jmp (var epc1)))
+d "rotw -1" f08040 0x0 nop
+d "round.s a2, f3, 1" 10238a 0x0 (set a2 (fbits (fround rna (*. rna (float 0 (var f3) ) (float 0 (bv 32 0x40000000) )))))
+d "rsil a1, 0xf" 106f00 0x0 (seq (set a1 (var ps)) (set ps (| (& (var ps) (~ (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x4)) false) (bv 32 0x0) false))) (& (<< (bv 32 0xf) (bv 32 0x0) false) (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x4)) false) (bv 32 0x0) false)))))
+d "rsqrt0.s f1, f2" a012fa 0x0 nop
+Bd "rsr" 100903 0 ()
+d "rsync" 102000 0x0 nop