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change indirect index logic
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taichi-ishitani committed Nov 22, 2024
1 parent dcd40f7 commit c357e19
Showing 1 changed file with 13 additions and 11 deletions.
24 changes: 13 additions & 11 deletions rggen_indirect_register.sv
Original file line number Diff line number Diff line change
@@ -1,23 +1,25 @@
module rggen_indirect_register #(
parameter bit READABLE = 1,
parameter bit WRITABLE = 1,
parameter int ADDRESS_WIDTH = 8,
parameter bit [ADDRESS_WIDTH-1:0] OFFSET_ADDRESS = '0,
parameter int BUS_WIDTH = 32,
parameter int DATA_WIDTH = BUS_WIDTH,
parameter int VALUE_WIDTH = BUS_WIDTH,
parameter int INDIRECT_INDEX_WIDTH = 1,
parameter bit [INDIRECT_INDEX_WIDTH-1:0] INDIRECT_INDEX_VALUE = '0
parameter bit READABLE = 1,
parameter bit WRITABLE = 1,
parameter int ADDRESS_WIDTH = 8,
parameter bit [ADDRESS_WIDTH-1:0] OFFSET_ADDRESS = '0,
parameter int BUS_WIDTH = 32,
parameter int DATA_WIDTH = BUS_WIDTH,
parameter int VALUE_WIDTH = BUS_WIDTH,
parameter int INDIRECT_MATCH_WIDTH = 1
)(
input logic i_clk,
input logic i_rst_n,
rggen_register_if.register register_if,
input logic [INDIRECT_INDEX_WIDTH-1:0] i_indirect_index,
input logic [INDIRECT_MATCH_WIDTH-1:0] i_indirect_match,
rggen_bit_field_if.register bit_field_if
);
logic index_matched;

assign index_matched = (i_indirect_index == INDIRECT_INDEX_VALUE) ? '1 : '0;
always_comb begin
index_matched = i_indirect_match == '1;
end

rggen_register_common #(
.READABLE (READABLE ),
.WRITABLE (WRITABLE ),
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