RZG3S_SMARC Hardware connection

Table of Contents

• Board set-up
• Debug connection
• Hardware connection for tests and samples

Followings are hardware connection for RZ/G3S SMARC Evaluation Kit, for more detail, please visit the following links

• RZ/G3S Evaluation Board Kit Quick Start Guide

• RZ/G3S Group User's Manual: Hardware

• SMARC EVK of RZ/G3S Linux Start-up Guide

Board set-up

RZ/G3S-SMARC is designed to start different systems on cores. It uses Yocto as the build system to build Linux system and boot loaders to run BL2 TF-A on Cortex-A55 System Core before starting Zephyr. The minimal steps are described below.

1. Follow ''2.2 Building Images'' of SMARC EVK of RZ/G3S Linux Start-up Guide to prepare the build environment.

2. Before build, add PLAT_M33_BOOT_SUPPORT=1 to meta-renesas/meta-rzg3s/recipes-bsp/trusted-firmware-a/trusted-firmware-a.bbappend.

   require trusted-firmware-a.inc
   COMPATIBLE_MACHINE_rzg3s = "(rzg3s-dev|smarc-rzg3s)"
   PLATFORM_rzg3s-dev = "g3s"
   EXTRA_FLAGS_rzg3s-dev = "BOARD=dev14_1_lpddr PLAT_SYSTEM_SUSPEND=vbat"
   PLATFORM_smarc-rzg3s = "g3s"
   EXTRA_FLAGS_smarc-rzg3s = "BOARD=smarc PLAT_SYSTEM_SUSPEND=vbat PLAT_M33_BOOT_SUPPORT=1"

3. Start the build:

   MACHINE=smarc-rzg3s bitbake core-image-minimal

   The below necessary artifacts will be located in the build/tmp/deploy/images

   Artifacts	File name
   Boot loader	bl2_bp_spi-smarc-rzg3s.srec fip-smarc-rzg3s.srec
   Flash Writer	FlashWriter-smarc-rzg3s.mot

4. Follow ''4.2 Startup Procedure'' of SMARC EVK of RZ/G3S Linux Start-up Guide for power supply and board setting at SCIF download (SW_MODE[1:4] = OFF, ON, OFF, ON) and Cortex-A55 cold boot (SW_CONFIG[1:6] = OFF, OFF, ON, OFF, OFF, OFF)

5. Follow ''4.3 Download Flash Writer to RAM'' of SMARC EVK of RZ/G3S Linux Start-up Guide to download Flash Writer to RAM

6. Follow ''4.4 Write the Bootloader'' of SMARC EVK of RZ/G3S Linux Start-up Guide to write the boot loader to the target board by using Flash Writer.

7. Before using flash command, the board must be set to Cortex-M33 cold boot (SW_CONFIG[1:6] = OFF, OFF, ON, OFF, OFF, ON) and SPI boot mode (SW_MODE[1:4] = OFF, OFF, OFF, ON). After flashing with west flash command, it must be set back to Cortex-A55 cold boot (SW_CONFIG[1:6] = OFF, OFF, ON, OFF, OFF, OFF) to run.

Debug connection

SW	Configurations
SW_MODE[1:4]	OFF, OFF, OFF, ON
SW_CONFIG[1:6]	OFF, OFF, ON, OFF, OFF, OFF

Hardware connection for tests and samples

An additional UART port is required for Cortex-M33 System Core. It can be accessed by connecting Pmod USBUART to the upper side of PMOD1_3A. The below image shows how to access the UART port of Cortex-M33 System Core via Pmod USBUART.

• Hardware connection for UART

hello_world (samples/hello_world): No additional connection.

zTest (tests/drivers/uart/uart_basic_api): No additional connection.

• Hardware connection for GPIO

zTest (tests/drivers/uart/uart_basic_api): No additional connection.

zTest (tests/drivers/gpio/gpio_api_1pin): No additional connection.

zTest (tests/drivers/gpio/gpio_basic_api): Connect pin P8_2 (Pmod1_6A, pin 9) to pin P8_3 (Pmod1_6A, pin 10)