Work converting all UUID::INVALID to Option

pc2 · Dec 19, 2023 · 7bd9167 · 7bd9167
1 parent bca3d75
commit 7bd9167
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Showing 10 changed files with 187 additions and 149 deletions.
diff --git a/src/ast.rs b/src/ast.rs
@@ -176,7 +176,7 @@ impl Module {
 }
 
 #[derive(Debug,Clone,Copy)]
-pub struct GlobalReference(pub Span, pub NamedUUID); // token index, and name span
+pub struct GlobalReference(pub Span, pub Option<NamedUUID>); // token index, and name span
 
 #[derive(Debug)]
 pub struct ASTRoot {

diff --git a/src/codegen_fallback.rs b/src/codegen_fallback.rs
@@ -42,10 +42,11 @@ pub fn value_to_str(value : &Value) -> String {
     }
 }
 
-pub fn gen_verilog_code(md : &Module, instance : &InstantiatedModule) -> Option<String> {
+pub fn gen_verilog_code(md : &Module, instance : &InstantiatedModule) -> String {
+    assert!(!instance.errors.did_error(), "Module cannot have experienced an error");
     let mut program_text : String = format!("module {}(\n\tinput clk, \n", md.link_info.name);
-    for (port, real_port) in zip(&md.interface.interface_wires, &instance.interface) {
-        if real_port.id == UUID::INVALID {return None;}
+    let submodule_interface = instance.interface.as_ref().unwrap();
+    for (port, real_port) in zip(&md.interface.interface_wires, submodule_interface) {
         let wire = &instance.wires[real_port.id];
         program_text.push_str(if port.is_input {"\tinput"} else {"\toutput /*mux_wire*/ reg"});
         program_text.push_str(&typ_to_verilog_array(&wire.typ));
@@ -64,7 +65,7 @@ pub fn gen_verilog_code(md : &Module, instance : &InstantiatedModule) -> Option<
             }
         }
         let wire_or_reg = if let RealWireDataSource::Multiplexer{is_state: initial_value, sources: _} = &w.source {
-            if let StateInitialValue::NotState = initial_value {
+            if let StateInitialValue::Combinatorial = initial_value {
                 "/*mux_wire*/ reg"
             } else {
                 "reg"
@@ -100,7 +101,8 @@ pub fn gen_verilog_code(md : &Module, instance : &InstantiatedModule) -> Option<
         program_text.push(' ');
         program_text.push_str(&sm.name);
         program_text.push_str("(\n.clk(clk)");
-        for (port, wire) in zip(&sm.instance.interface, &sm.wires) {
+        let Some(sm_interface) = &sm.instance.interface else {unreachable!()}; // Having an invalid interface in a submodule is an error! This should have been caught before!
+        for (port, wire) in zip(sm_interface, &sm.wires) {
             program_text.push_str(",\n.");
             program_text.push_str(&sm.instance.wires[port.id].name);
             program_text.push('(');
@@ -116,7 +118,7 @@ pub fn gen_verilog_code(md : &Module, instance : &InstantiatedModule) -> Option<
             RealWireDataSource::Multiplexer { is_state, sources } => {
                 let output_name = w.name.deref();
                 match is_state {
-                    StateInitialValue::NotState => {
+                    StateInitialValue::Combinatorial => {
                         program_text.push_str(&format!("/*always_comb*/ always @(*) begin\n\t{output_name} <= 1'bX; // Not defined when not valid\n"));
                     }
                     StateInitialValue::State{initial_value : _} => {
@@ -135,8 +137,8 @@ pub fn gen_verilog_code(md : &Module, instance : &InstantiatedModule) -> Option<
                         }
                     }
                     let from_name = instance.wires[s.from.from].name.deref();
-                    if s.from.condition != UUID::INVALID {
-                        let cond = instance.wires[s.from.condition].name.deref();
+                    if let Some(cond) = s.from.condition {
+                        let cond = instance.wires[cond].name.deref();
                         program_text.push_str(&format!("\tif({cond}) begin {output_name}{path} <= {from_name}; end\n"));
                     } else {
                         program_text.push_str(&format!("\t{output_name}{path} <= {from_name};\n"));
@@ -153,5 +155,5 @@ pub fn gen_verilog_code(md : &Module, instance : &InstantiatedModule) -> Option<
 
     program_text.push_str("endmodule\n");
 
-    Some(program_text)
+    program_text
 }
diff --git a/src/dev_aid/syntax_highlighting.rs b/src/dev_aid/syntax_highlighting.rs
@@ -134,8 +134,8 @@ fn walk_name_color(all_objects : &[NamedUUID], links : &Links, result : &mut [ID
             result[name_part].typ = IDETokenType::Identifier(ide_typ);
         }
         for GlobalReference(reference_span, ref_uuid) in &link_info.global_references {
-            let typ = if *ref_uuid != NamedUUID::INVALID {
-                IDETokenType::Identifier(links.globals[*ref_uuid].get_ide_type())
+            let typ = if let Some(id) = ref_uuid {
+                IDETokenType::Identifier(links.globals[*id].get_ide_type())
             } else {
                 IDETokenType::Invalid
             };