Add Support for Digilent Arty-A7 100T FPGA Board

[WorldofJARcraft]

This patch adds support for the Arty A7 FPGA (#154).

Overview

• Adds support for Arty A7 100T FPGA variant, running CVA6 at 25 MHz
• Connects debug module via built-in USB-JTAG
• Connects USB UART
• SPI/SD via JA PMOD
• Adds cv64a6_imac configuration
• Tested with Xilinx Vivado v2023.2

Changed

• Added constraints and configurations for Arty A7
• Backported BSCANE2 probe for debug interface from riscv-dbg. I have placed the updated files in a separate directory, they are only ever compiled when building for the A7. Simulation, ASIC flows and other FPGA boards continue to use the current version of riscv-dbg.
• Backported common-cells needed for BSCANE2 debug. Not used when building anything except ARTY A7.

What I have been able to test so far:

• Design meets timing for cv32a6_imac_sv32 @ 25 MHz
• bootrom runs and detects that no SD card exists
• debugging via openocd/gdb works via the built-in USB JTAG
• zephyr hello-world example can be loaded and debugged via west debug and west flash in both 32 and 64 bit configs and runs as expected (zephyr PR coming soon)
• Resetting the CPU with the "Reset" button
• USB UART output works
• A reduced 64-bit config (cv64imac) fits the board, meets timing and runs a hello world example with zephyr. I have added it to the PR.
• A cv64imafdc_fpga configuration, in which I have enabled CVA6ConfigFpgaEn, i.e., inferring memories as block RAM, meets timing and fits the board with appx. 5000 LUTs to spare.

What I have not yet tested:

• Booting Linux, I will have to order a microSD pmod before I can test this.
• Other Arty variants (e.g., S7, A7-35T).

What does not work:

• Full cv64a6_imafdc_sv39 config (i.e., without CVA6ConfigFpgaEn) does not fit the board, uses appx. 1000 LUTs too much. Might fit when sacrificing a peripheral (e.g., debug, SPI, GPIO, ...)
• Ethernet support due to timing/resource constraints (but could possibly fit with 32 bit SoCs)

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