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[Pmp] Verif plan TXT #2457

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CoralieAllioux
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This PR aims at resolving task #1447

Here's a first version of the Verification Plan of PMP, in txt format.
It is split in 2 files:

  • verif/docs/VerifPlans/PMP/pmp_verif_plan.txt
  • verif/docs/VerifPlans/PMP/pmp_verif_plan_features.txt

VPTool format is undergoing on our side.
We'd like to share already the content to get first feedbacks.

cathales and others added 30 commits July 10, 2024 23:33
Specify CV-X-IF version supported: 1.0.0.
Mention of B extension (with includes the Zb* extensions, already in the specification).
Make FENCE.T as a "should" instead of "shall" as we do not have plans to integrate it yet.
…Factorization algorithm , improve csr_updater.yaml, add spike support (openhwgroup#2372)
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github-actions bot commented Nov 8, 2024

✔️ successful run, report available here.

@OlivierBetschi
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Added to this pull request are some PMP tests along with the Verif Plan integrated in VP_TOOL. Weird that CI is failing as no RTL has been updated and the PMP tests are not integrated into the regression scripts

dependabot bot and others added 24 commits November 12, 2024 07:10
…p#2587)

If Hypervisor extension is enabled, the logic required to properly trap to S mode is currently excluded. Fix this by adjusting the if block.
The simu-gate ci job was broken since a while. This PR fixes it.
Add failures checks in `.gitlab-ci/scripts/report_tandem.py`:
* catch wrong or missing log directory
* catch wrong yaml reports
First step to add FpgaAltera optimization parameter
* Fill docs/design/design-manual/source/cva6_issue_stage.adoc
* Add variables to docs/design/design-manual/source/design.adoc
* Update port doc comments in core/issue_stage.sv, core/issue_read_operands.sv and core/scoreboard.sv
…p#2599)

If Hypervisor extension is enabled, the logic required to properly trap
to S mode is currently excluded. Fix this by adjusting the if block.
The first optimization for Altera FPGA is to move the instruction queue to LUTRAM. The reason why the optimization previously done for Xilinx is not working, is that in that case asynchronous RAM primitives are used, and Altera does not support asynchronous RAM. Therefore, this optimization consists in using synchronous RAM for the instruction queue and FIFOs inside wt axi adapter.

The main changes to the existing code are:

New RAM module to infer synchronous RAM in altera with independent read and write ports (SyncDpRam_ind_r_w.sv)

Changes inside cva6_fifo_v3 to adapt to the use of synchronous RAM instead of asynchronous:

When the FIFO is not empty, next data is always read and available at the output hiding the reading latency introduced by synchronous RAM (similar to fall-through approach). This is a simplification that is possible because in a FIFO we always know what is the next address to be read.

When data is read right after write, we can’t use the previous method because there is a latency to first write the data in the FIFO, and then to read it. For this reason, in the new design there is an auxiliary register used to hide this latency. This is used only if the FIFO is empty, so we detect when the word written is first word, and keep it in this register. If the next cycle comes a read, the data out is taken from the aux register. Afterwards the data is already available in the RAM and can be read continuously as in the first case.

All this is only used inf FpgaAlteraEn parameter is enabled, otherwise the previous implementation with asynchronous RAM applies (when FpgaEn is set), or the register based implementation (when FpgaEn is not set).
* Disable tandem on riscv-tests-v testlist
* More relevant error message on report tandem script
Related issue: openhwgroup#2605
…2621)

* cva6 refactor & cleanup to enable tandem reports generation for elf tests such as testelf for simu-gate:
   1. merge redundant functions to run directed tests in `cva6.py` (`run_c`, `run_elf`, `run_assembly` -> `run_test`)
   2. removed broken and unused functions by the way (`run_c_from_dir`, `run_assembly_from_dir`)
* collect sim reports of simu-gate job to display them in the cva6 dashboard : ⚠️ the simu gate job will still fail but the result on the dashboard will be accurate and will allow debugging
Integrating the modifications to the AXI agent made by CEA
…ly. (openhwgroup#2624)

Update riscv-config spec files and Spike Yaml file for CV32A65X.

Bump CVV to change Spike default PMP granularity to 8 and to include corresponding Spike Yaml parameter.
The second optimization for Altera FPGA is to move the BHT to LUTRAM. Same as before, the reason why the optimization previously done for Xilinx is not working, is that in that case asynchronous RAM primitives are used, and Altera does not support asynchronous RAM. Therefore, this optimization consists in using synchronous RAM for the BHT.

The main changes to the existing code are:

New RAM module to infer synchronous RAM in altera with 2 independent read ports and one write port (SyncThreePortRam.sv)

Changes in the frontend.sv file: modify input to vpc_i port of BHT, by advancing the address to read, in order to compensate for the delay of synchronous RAM.

Changes in the bht.sv file: This case is more complex because of the logic operations that need to be performed inside the BHT. First, the pc pointed by bht_update_i is read from the memory, modified according to the saturation counter and valid bit, and finally written again in the memory. The prediction output is given based on the vpc_i. With asynchronous memory, the new data written via update_i is available one clock cycle after writing it. So, if vpc_i tries to read the address that was previously written by update_i, everything is fine. However, in the case of synchronous memory there are three clock cycles of latency (one for reading the pc content (read port 1), another one for writing it, and another one for reading in the other port (read port 0)). For this reason, there is the need to adapt the design to these new latency constraints:

First, there is the need for a delay on the address write of the synchronous RAM, to wait for the previous pc read and store the right modified data.

Once this is solved, similarly to the FIFO case, there is the need for an auxiliary buffer that will store the data written in the FIFO, allowing to have it available 2 clock cycles after the update_i was valid. This is because after having the correct data, the RAM takes 2 clock cycles until data can be available in the output (one clock cycle for writing and one for reading).

Finally, there is a multiplexer in the output that permits to deliver the correct prediction providing the data from the update logic (1 cycle of delay), the auxiliary register (2 cycles of delay), or the RAM (3 or more cycles of delay), depending on the delay since the update_i was valid (i.e. written to the memory).
…group#2627)

CSR are no more described in CV32A6_Control_Status_Registers.html
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✔️ successful run, report available here.

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