fix simu gate step 1: cva6.py refactor & collect report (#2621)

* cva6 refactor & cleanup to enable tandem reports generation for elf tests such as testelf for simu-gate:
   1. merge redundant functions to run directed tests in `cva6.py` (`run_c`, `run_elf`, `run_assembly` -> `run_test`)
   2. removed broken and unused functions by the way (`run_c_from_dir`, `run_assembly_from_dir`)
* collect sim reports of simu-gate job to display them in the cva6 dashboard : ⚠️ the simu gate job will still fail but the result on the dashboard will be accurate and will allow debugging

.gitlab-ci.yml

@@ -538,6 +538,7 @@ simu-gate:
     SIMU_PERIOD: "20"  # 50 Mhz
     PERIOD: "15"  # 66 Mhz
   script:
+    - mkdir -p artifacts/{reports,logs}
     - git -C verif/core-v-verif fetch --unshallow
     - !reference [.copy_spike_artifacts]
     - echo $PERIOD
@@ -553,12 +554,15 @@ simu-gate:
     - mkdir -p pd/synth/${TOP}_${DV_TARGET}/outputs/
     - export DV_SIMULATORS="spike"
     - bash verif/regress/${PROG_NAME}.sh
-    - cp verif/sim/out_*/directed_c_tests/*.o verif/sim/testelf.o
+    - cp verif/sim/out_*/directed_tests/*.o verif/sim/testelf.o
     - python3 ${SYNTH_SCRIPT_PATH}/scharm -p configs/modules/CVA6.yml --runner=True --compaign="simu-gate" --name=testelf
     - grep "Simulation terminated" verif/sim/out_*/*/*.log.iss
     - mv ${SYNTH_SCRIPT_PATH}/artifacts/ artifacts/artifacts_gate/
     - rm artifacts/artifacts_gate/*/build/*.fsdb
-  after_script: *simu_after_script
+    - mkdir -p verif/sim/out_reports
+    - mkdir -p artifacts/sim_artifacts
+    - for i in verif/sim/out*/vcs-uvm-gate*/*; do cp $i $(dirname $(dirname $i))/vcs-uvm_sim/gate.$(basename $i); done
+    - python3 .gitlab-ci/scripts/report_tandem.py verif/sim/out*/vcs-uvm_sim
 
 fpga-boot:
   extends: