Merge pull request #1 from jsorg71/test-asm

change diff_rlgr1/3 to match rlgr1/3 on ending bits
neutrinolabs · Mar 28, 2017 · 3d24a7e · 3d24a7e
2 parents a0a9eb7 + f509a34
commit 3d24a7e
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diff --git a/src/rfxencode_diff_rlgr1.c b/src/rfxencode_diff_rlgr1.c
@@ -240,6 +240,7 @@ rfx_encode_diff_rlgr1(sint16 *coef, uint8 *cdata, int cdata_size)
     if (bit_count > 0)
     {
         bits <<= 8 - bit_count;
+        bits |= ((1 << (8 - bit_count)) - 1) & *cdata;
         *cdata = bits;
         cdata++;
         bit_count = 0;

diff --git a/src/rfxencode_diff_rlgr3.c b/src/rfxencode_diff_rlgr3.c
@@ -277,6 +277,7 @@ rfx_encode_diff_rlgr3(sint16 *coef, uint8 *cdata, int cdata_size)
     if (bit_count > 0)
     {
         bits <<= 8 - bit_count;
+        bits |= ((1 << (8 - bit_count)) - 1) & *cdata;
         *cdata = bits;
         cdata++;
         bit_count = 0;