Skip to content

[dv] Add spurious responses to memory agent #185

[dv] Add spurious responses to memory agent

[dv] Add spurious responses to memory agent #185

Triggered via pull request July 3, 2024 19:58
Status Failure
Total duration 49s
Artifacts

pr_lint.yml

on: pull_request
verible-lint
41s
verible-lint
Fit to window
Zoom out
Zoom in

Annotations

1 error and 4 warnings
verible-lint
Process completed with exit code 1.
verible-lint: dv/uvm/core_ibex/tb/core_ibex_tb_top.sv#L171
[verible-verilog-lint] reported by reviewdog 🐶 Line length exceeds max: 100; is: 123 [Style: line-length] [line-length] Raw Output: message:"Line length exceeds max: 100; is: 123 [Style: line-length] [line-length]" location:{path:"./dv/uvm/core_ibex/tb/core_ibex_tb_top.sv" range:{start:{line:171 column:101}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}
verible-lint: dv/uvm/core_ibex/tb/core_ibex_tb_top.sv#L172
[verible-verilog-lint] reported by reviewdog 🐶 Line length exceeds max: 100; is: 112 [Style: line-length] [line-length] Raw Output: message:"Line length exceeds max: 100; is: 112 [Style: line-length] [line-length]" location:{path:"./dv/uvm/core_ibex/tb/core_ibex_tb_top.sv" range:{start:{line:172 column:101}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}
verible-lint: dv/uvm/core_ibex/tb/core_ibex_tb_top.sv#L173
[verible-verilog-lint] reported by reviewdog 🐶 Line length exceeds max: 100; is: 106 [Style: line-length] [line-length] Raw Output: message:"Line length exceeds max: 100; is: 106 [Style: line-length] [line-length]" location:{path:"./dv/uvm/core_ibex/tb/core_ibex_tb_top.sv" range:{start:{line:173 column:101}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}
verible-lint: dv/uvm/core_ibex/tb/core_ibex_tb_top.sv#L176
[verible-verilog-lint] reported by reviewdog 🐶 Line length exceeds max: 100; is: 156 [Style: line-length] [line-length] Raw Output: message:"Line length exceeds max: 100; is: 156 [Style: line-length] [line-length]" location:{path:"./dv/uvm/core_ibex/tb/core_ibex_tb_top.sv" range:{start:{line:176 column:101}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}