Sail is a language for describing the instruction-set architecture (ISA) semantics of processors. Sail aims to provide a engineer-friendly, vendor-pseudocode-like language for describing instruction semantics. It is essentially a first-order imperative language, but with lightweight dependent typing for numeric types and bitvector lengths, which are automatically checked using Z3. It has been used for several papers, available from http://www.cl.cam.ac.uk/~pes20/sail/.
Given a Sail definition, the tool will type-check it and generate executable emulators, in C and OCaml, theorem-prover definitions for Isabelle, HOL4, and Coq, and definitions to integrate with our RMEM and isla-axiomatic tools for concurrency semantics. This is all work in progress, and some theorem-prover definitions do not yet work for the more complex models; see the most recent papers and the ARMv8.5-A model for descriptions of the current state.
This repository contains the implementation of Sail, together with some Sail specifications and related tools.
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A manual, manual.pdf with source (in doc/)
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The Sail source code (in src/)
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Generated Isabelle snapshots of some ISA models, in snapshots/isabelle
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Documentation for generating Isabelle and working with the ISA specs in Isabelle in snapshots/isabelle/Manual.pdf
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A simple emacs mode with syntax highlighting (in editors/)
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A test suite for Sail (in test/)
Sail is currently being used for Arm, RISC-V, MIPS, CHERI-MIPS, IBM Power, and x86 models, variously ranging from full definitions to core user-mode fragments, and either here or in separate repositories:
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Sail Armv8.3-A ISA model. This is the "public" model described in our POPL 2019 paper, now largely superseded by the above.
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Sail Armv8-A ISA model, handwritten. This is a handwritten user-mode fragment.
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Sail IBM POWER ISA model, automatically generated from IBM XML documentation. This is a user-mode fragment.
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Sail x86 ISA model, handwritten. This is a handwritten user-mode fragment.
The hand-written IBM POWER, and x86 models are currently not in sync with the latest version of Sail, which is the (default) sail2 branch on Github. These and the RISC-V model are integrated with our RMEM tool for concurrency semantics.
- Sail 32-bit RISC-V model, partially handwritten and partially generated. This currently implements a fragment of the machine mode (-M) specification for RV32IM. (Developed independently of the full RISC-V model for the REMS project.)
See INSTALL.md for how to install Sail using opam (recommended).
See BUILDING.md for full details of how to build Sail from source with all the required dependencies.
editors/sail-mode.el contains an Emacs mode for the most recent version of Sail which provides some basic syntax highlighting.
editors/vscode contains a Visual Studio Code mode which provides some basic syntax highlighting. It is also available on the VSCode Marketplace.
editors/vscode/sail contains a Visual Studio Code
mode which provides some basic syntax highlighting. CLion/PyCharm can also
parse the editors/vscode/sail/syntax/sail.tmLanguage.json
file and use it to provide basic syntax highlighting.
To install open Preferences > Editor > TextMate Bundles. On that settings
page press the + icon and locate the editors/vscode/sail
directory.
This requires the TextMate Bundles plugin.
The Sail implementation, in src/, as well as its tests in test/ and other supporting files in lib/ and language/, is distributed under the 2-clause BSD licence in the headers of those files and in src/LICENCE.
The generated parts of the ASL-derived Armv8.5 and Armv8.3 models are copyright Arm Ltd, and distributed under a BSD Clear licence. See https://github.com/meriac/archex, and the README file in that directory.
The hand-written Armv8 model, in arm/, is distributed under the 2-clause BSD licence in the headers of those files.
The x86 model in x86/ is distributed under the 2-clause BSD licence in the headers of those files.
The POWER model in power/ is distributed under the 2-clause BSD licence in the headers of those files.
The models in separate repositories are licensed as described in each.
This work was partially supported by EPSRC grant EP/K008528/1 REMS: Rigorous Engineering for Mainstream Systems, an ARM iCASE award, EPSRC IAA KTF funding, and donations from Arm. This project has received funding from the European Research Council (ERC) under the European Union’s Horizon 2020 research and innovation programme (grant agreement No 789108, ELVER).
Approved for public release; distribution is unlimited. This research is sponsored by the Defense Advanced Research Projects Agency (DARPA) and the Air Force Research Laboratory (AFRL), under contracts FA8750-10-C-0237 ("CTSRD") and FA8650-18-C-7809 ("CIFV"). The views, opinions, and/or findings contained in these articles OR presentations are those of the author(s)/presenter(s) and should not be interpreted as representing the official views or policies of the Department of Defense or the U.S. Government.