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Cores affected Cores affected #1461: Scheduled
November 8, 2024 00:10 1m 4s master
master
November 8, 2024 00:10 1m 4s
wc: obj working in simulation but not on FPGA Verilator linter #1868: Commit f4d9ab3 pushed by jotego
November 7, 2024 07:04 3m 34s master
master
November 7, 2024 07:04 3m 34s
wc: obj working in simulation but not on FPGA Cores affected #1460: Commit f4d9ab3 pushed by jotego
November 7, 2024 07:04 1m 19s master
master
November 7, 2024 07:04 1m 19s
Verilator linter Verilator linter #1867: Scheduled
November 7, 2024 00:24 28m 54s master
master
November 7, 2024 00:24 28m 54s
Compile all Compile all #595: Scheduled
November 7, 2024 00:12 1h 16m 45s master
master
November 7, 2024 00:12 1h 16m 45s
Cores affected Cores affected #1459: Scheduled
November 7, 2024 00:10 1m 3s master
master
November 7, 2024 00:10 1m 3s
wc: obj module -wip- Verilator linter #1866: Commit 349a052 pushed by jotego
November 6, 2024 07:39 3m 14s master
master
November 6, 2024 07:39 3m 14s
wc: obj module -wip- Cores affected #1458: Commit 349a052 pushed by jotego
November 6, 2024 07:39 1m 8s master
master
November 6, 2024 07:39 1m 8s
Verilator linter Verilator linter #1865: Scheduled
November 6, 2024 00:23 28m 46s master
master
November 6, 2024 00:23 28m 46s
Compile all Compile all #594: Scheduled
November 6, 2024 00:11 31m 14s master
master
November 6, 2024 00:11 31m 14s
Cores affected Cores affected #1457: Scheduled
November 6, 2024 00:10 1m 4s master
master
November 6, 2024 00:10 1m 4s
Removed horizontal delay in jtframe_tilemap when flip==1 (#863) Cores affected #1456: Commit 79158aa pushed by jotego
November 5, 2024 18:14 1m 17s master
master
November 5, 2024 18:14 1m 17s
Removed horizontal delay in jtframe_tilemap when flip==1 (#863) Verilator linter #1864: Commit 79158aa pushed by jotego
November 5, 2024 18:14 3m 41s master
master
November 5, 2024 18:14 3m 41s
Removed horizontal delay in jtframe_tilemap when flip==1 Debug builds (SiDi128) #153: Pull request #863 opened by rp-jt
November 5, 2024 15:18 1h 16m 10s 1942-flip
1942-flip
November 5, 2024 15:18 1h 16m 10s
Removed horizontal delay in jtframe_tilemap when flip==1 Compile all #593: Pull request #863 opened by rp-jt
November 5, 2024 15:18 1h 18m 42s 1942-flip
1942-flip
November 5, 2024 15:18 1h 18m 42s
Removed horizontal delay in jtframe_tilemap when flip==1 Verilator linter #1863: Pull request #863 opened by rp-jt
November 5, 2024 15:18 3m 37s 1942-flip
1942-flip
November 5, 2024 15:18 3m 37s
wc: corrected HS and VS to center image on screen (#862) Cores affected #1455: Commit 8e0ee05 pushed by jotego
November 5, 2024 10:46 19m 53s master
master
November 5, 2024 10:46 19m 53s
wc: corrected HS and VS to center image on screen (#862) Verilator linter #1862: Commit 8e0ee05 pushed by jotego
November 5, 2024 10:46 22m 47s master
master
November 5, 2024 10:46 22m 47s
wc: corrected HS and VS to center image on screen Verilator linter #1861: Pull request #862 opened by rp-jt
November 5, 2024 10:05 3m 34s wc-center
wc-center
November 5, 2024 10:05 3m 34s
wc: corrected HS and VS to center image on screen Compile all #592: Pull request #862 opened by rp-jt
November 5, 2024 10:05 1h 18m 46s wc-center
wc-center
November 5, 2024 10:05 1h 18m 46s
wc: corrected HS and VS to center image on screen Debug builds (SiDi128) #152: Pull request #862 opened by rp-jt
November 5, 2024 10:05 1h 20m 45s wc-center
wc-center
November 5, 2024 10:05 1h 20m 45s
wc: boots correctly. Thanks to Gyurco for spotting the problem. Fixes… Cores affected #1454: Commit b5c0015 pushed by jotego
November 5, 2024 06:08 1m 10s master
master
November 5, 2024 06:08 1m 10s
wc: boots correctly. Thanks to Gyurco for spotting the problem. Fixes… Verilator linter #1860: Commit b5c0015 pushed by jotego
November 5, 2024 06:08 3m 40s master
master
November 5, 2024 06:08 3m 40s
Verilator linter Verilator linter #1859: Scheduled
November 5, 2024 00:24 39m 55s master
master
November 5, 2024 00:24 39m 55s
Compile all Compile all #591: Scheduled
November 5, 2024 00:11 1h 6m 26s master
master
November 5, 2024 00:11 1h 6m 26s