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Removed horizontal delay in jtframe_tilemap when flip==1
Compile all #593: Pull request #863 opened by rp-jt
November 5, 2024 15:18 1h 18m 42s 1942-flip
November 5, 2024 15:18 1h 18m 42s
Removed horizontal delay in jtframe_tilemap when flip==1
Verilator linter #1863: Pull request #863 opened by rp-jt
November 5, 2024 15:18 3m 37s 1942-flip
November 5, 2024 15:18 3m 37s
wc: corrected HS and VS to center image on screen (#862)
Cores affected #1455: Commit 8e0ee05 pushed by jotego
November 5, 2024 10:46 19m 53s master
November 5, 2024 10:46 19m 53s
wc: corrected HS and VS to center image on screen (#862)
Verilator linter #1862: Commit 8e0ee05 pushed by jotego
November 5, 2024 10:46 22m 47s master
November 5, 2024 10:46 22m 47s
wc: corrected HS and VS to center image on screen
Verilator linter #1861: Pull request #862 opened by rp-jt
November 5, 2024 10:05 3m 34s wc-center
November 5, 2024 10:05 3m 34s
wc: corrected HS and VS to center image on screen
Compile all #592: Pull request #862 opened by rp-jt
November 5, 2024 10:05 1h 18m 46s wc-center
November 5, 2024 10:05 1h 18m 46s
wc: corrected HS and VS to center image on screen
Debug builds (SiDi128) #152: Pull request #862 opened by rp-jt
November 5, 2024 10:05 1h 20m 45s wc-center
November 5, 2024 10:05 1h 20m 45s
wc: boots correctly. Thanks to Gyurco for spotting the problem. Fixes…
Cores affected #1454: Commit b5c0015 pushed by jotego
November 5, 2024 06:08 1m 10s master
November 5, 2024 06:08 1m 10s
wc: boots correctly. Thanks to Gyurco for spotting the problem. Fixes…
Verilator linter #1860: Commit b5c0015 pushed by jotego
November 5, 2024 06:08 3m 40s master
November 5, 2024 06:08 3m 40s
Verilator linter
Verilator linter #1859: Scheduled
November 5, 2024 00:24 39m 55s master
November 5, 2024 00:24 39m 55s
Compile all
Compile all #591: Scheduled
November 5, 2024 00:11 1h 6m 26s master
November 5, 2024 00:11 1h 6m 26s
Cores affected
Cores affected #1453: Scheduled
November 5, 2024 00:10 1m 20s master
November 5, 2024 00:10 1m 20s
wc sch: sub CPU address bus connection to shared memory
Verilator linter #1858: Commit 51b1a3e pushed by jotego
November 4, 2024 20:48 3m 43s master
November 4, 2024 20:48 3m 43s
wc sch: sub CPU address bus connection to shared memory
Cores affected #1452: Commit 51b1a3e pushed by jotego
November 4, 2024 20:48 1m 17s master
November 4, 2024 20:48 1m 17s
wc: scroll visible (scene 3)
Verilator linter #1857: Commit 0c115ef pushed by jotego
November 4, 2024 07:10 3m 13s master
November 4, 2024 07:10 3m 13s
wc: scroll visible (scene 3)
Cores affected #1451: Commit 0c115ef pushed by jotego
November 4, 2024 07:10 1m 0s master
November 4, 2024 07:10 1m 0s
Verilator linter
Verilator linter #1856: Scheduled
November 4, 2024 00:25 27m 48s master
November 4, 2024 00:25 27m 48s
Compile all
Compile all #590: Scheduled
November 4, 2024 00:12 1h 15m 12s master
November 4, 2024 00:12 1h 15m 12s
Cores affected
Cores affected #1450: Scheduled
November 4, 2024 00:11 1m 2s master
November 4, 2024 00:11 1m 2s
wc: tehkanwch shows the grid screen but then halts
Verilator linter #1855: Commit a2b4ca8 pushed by jotego
November 3, 2024 17:19 3m 23s master
November 3, 2024 17:19 3m 23s
wc: tehkanwch shows the grid screen but then halts
Cores affected #1449: Commit a2b4ca8 pushed by jotego
November 3, 2024 17:19 1m 1s master
November 3, 2024 17:19 1m 1s
Verilator linter
Verilator linter #1854: Scheduled
November 3, 2024 00:26 26m 41s master
November 3, 2024 00:26 26m 41s
Compile all
Compile all #589: Scheduled
November 3, 2024 00:13 24m 34s master
November 3, 2024 00:13 24m 34s
Cores affected
Cores affected #1448: Scheduled
November 3, 2024 00:11 1m 2s master
November 3, 2024 00:11 1m 2s
wc: all modules connected
Verilator linter #1853: Commit 10228e0 pushed by jotego
November 2, 2024 17:24 3m 32s master
November 2, 2024 17:24 3m 32s