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| Original file line number | Diff line number | Diff line change |
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| /* | ||
| * @brief CGU/CCU registers and control functions | ||
| * | ||
| * @note | ||
| * Copyright(C) NXP Semiconductors, 2012 | ||
| * All rights reserved. | ||
| * | ||
| * @par | ||
| * Software that is described herein is for illustrative purposes only | ||
| * which provides customers with programming information regarding the | ||
| * LPC products. This software is supplied "AS IS" without any warranties of | ||
| * any kind, and NXP Semiconductors and its licensor disclaim any and | ||
| * all warranties, express or implied, including all implied warranties of | ||
| * merchantability, fitness for a particular purpose and non-infringement of | ||
| * intellectual property rights. NXP Semiconductors assumes no responsibility | ||
| * or liability for the use of the software, conveys no license or rights under any | ||
| * patent, copyright, mask work right, or any other intellectual property rights in | ||
| * or to any products. NXP Semiconductors reserves the right to make changes | ||
| * in the software without notification. NXP Semiconductors also makes no | ||
| * representation or warranty that such application will be suitable for the | ||
| * specified use without further testing or modification. | ||
| * | ||
| * @par | ||
| * Permission to use, copy, modify, and distribute this software and its | ||
| * documentation is hereby granted, under NXP Semiconductors' and its | ||
| * licensor's relevant copyrights in the software, without fee, provided that it | ||
| * is used in conjunction with NXP Semiconductors microcontrollers. This | ||
| * copyright, permission, and disclaimer notice must appear in all copies of | ||
| * this code. | ||
| */ | ||
|
|
||
| #ifndef __CGUCCU_18XX_43XX_H_ | ||
| #define __CGUCCU_18XX_43XX_H_ | ||
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| #include "chip_clocks.h" | ||
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| #ifdef __cplusplus | ||
| extern "C" { | ||
| #endif | ||
|
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| /** @ingroup CLOCK_18XX_43XX | ||
| * @{ | ||
| */ | ||
|
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| /** | ||
| * Audio or USB PLL selection | ||
| */ | ||
| typedef enum CHIP_CGU_USB_AUDIO_PLL { | ||
| CGU_USB_PLL, | ||
| CGU_AUDIO_PLL | ||
| } CHIP_CGU_USB_AUDIO_PLL_T; | ||
|
|
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| /** | ||
| * PLL register block | ||
| */ | ||
| typedef struct { | ||
| __I uint32_t PLL_STAT; /*!< PLL status register */ | ||
| __IO uint32_t PLL_CTRL; /*!< PLL control register */ | ||
| __IO uint32_t PLL_MDIV; /*!< PLL M-divider register */ | ||
| __IO uint32_t PLL_NP_DIV; /*!< PLL N/P-divider register */ | ||
| } CGU_PLL_REG_T; | ||
|
|
||
| /** | ||
| * @brief LPC18XX/43XX CGU register block structure | ||
| */ | ||
| typedef struct { /*!< (@ 0x40050000) CGU Structure */ | ||
| __I uint32_t RESERVED0[5]; | ||
| __IO uint32_t FREQ_MON; /*!< (@ 0x40050014) Frequency monitor register */ | ||
| __IO uint32_t XTAL_OSC_CTRL; /*!< (@ 0x40050018) Crystal oscillator control register */ | ||
| CGU_PLL_REG_T PLL[CGU_AUDIO_PLL + 1]; /*!< (@ 0x4005001C) USB and audio PLL blocks */ | ||
| __IO uint32_t PLL0AUDIO_FRAC; /*!< (@ 0x4005003C) PLL0 (audio) */ | ||
| __I uint32_t PLL1_STAT; /*!< (@ 0x40050040) PLL1 status register */ | ||
| __IO uint32_t PLL1_CTRL; /*!< (@ 0x40050044) PLL1 control register */ | ||
| __IO uint32_t IDIV_CTRL[CLK_IDIV_LAST];/*!< (@ 0x40050048) Integer divider A-E control registers */ | ||
| __IO uint32_t BASE_CLK[CLK_BASE_LAST]; /*!< (@ 0x4005005C) Start of base clock registers */ | ||
| } LPC_CGU_T; | ||
|
|
||
| /** | ||
| * @brief CCU clock config/status register pair | ||
| */ | ||
| typedef struct { | ||
| __IO uint32_t CFG; /*!< CCU clock configuration register */ | ||
| __I uint32_t STAT; /*!< CCU clock status register */ | ||
| } CCU_CFGSTAT_T; | ||
|
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| /** | ||
| * @brief CCU1 register block structure | ||
| */ | ||
| typedef struct { /*!< (@ 0x40051000) CCU1 Structure */ | ||
| __IO uint32_t PM; /*!< (@ 0x40051000) CCU1 power mode register */ | ||
| __I uint32_t BASE_STAT; /*!< (@ 0x40051004) CCU1 base clocks status register */ | ||
| __I uint32_t RESERVED0[62]; | ||
| CCU_CFGSTAT_T CLKCCU[CLK_CCU1_LAST]; /*!< (@ 0x40051100) Start of CCU1 clock registers */ | ||
| } LPC_CCU1_T; | ||
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| /** | ||
| * @brief CCU2 register block structure | ||
| */ | ||
| typedef struct { /*!< (@ 0x40052000) CCU2 Structure */ | ||
| __IO uint32_t PM; /*!< (@ 0x40052000) Power mode register */ | ||
| __I uint32_t BASE_STAT; /*!< (@ 0x40052004) CCU base clocks status register */ | ||
| __I uint32_t RESERVED0[62]; | ||
| CCU_CFGSTAT_T CLKCCU[CLK_CCU2_LAST - CLK_CCU1_LAST]; /*!< (@ 0x40052100) Start of CCU2 clock registers */ | ||
| } LPC_CCU2_T; | ||
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| /** | ||
| * @} | ||
| */ | ||
|
|
||
| #ifdef __cplusplus | ||
| } | ||
| #endif | ||
|
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||
| #endif /* __CGUCCU_18XX_43XX_H_ */ |
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| /* | ||
| * @brief Chip inclusion selector file | ||
| * | ||
| * Copyright(C) NXP Semiconductors, 2013 | ||
| * All rights reserved. | ||
| * | ||
| * Software that is described herein is for illustrative purposes only | ||
| * which provides customers with programming information regarding the | ||
| * LPC products. This software is supplied "AS IS" without any warranties of | ||
| * any kind, and NXP Semiconductors and its licensor disclaim any and | ||
| * all warranties, express or implied, including all implied warranties of | ||
| * merchantability, fitness for a particular purpose and non-infringement of | ||
| * intellectual property rights. NXP Semiconductors assumes no responsibility | ||
| * or liability for the use of the software, conveys no license or rights under any | ||
| * patent, copyright, mask work right, or any other intellectual property rights in | ||
| * or to any products. NXP Semiconductors reserves the right to make changes | ||
| * in the software without notification. NXP Semiconductors also makes no | ||
| * representation or warranty that such application will be suitable for the | ||
| * specified use without further testing or modification. | ||
| * | ||
| * Permission to use, copy, modify, and distribute this software and its | ||
| * documentation is hereby granted, under NXP Semiconductors' and its | ||
| * licensor's relevant copyrights in the software, without fee, provided that it | ||
| * is used in conjunction with NXP Semiconductors microcontrollers. This | ||
| * copyright, permission, and disclaimer notice must appear in all copies of | ||
| * this code. | ||
| */ | ||
|
|
||
| #ifndef __CHIP_H_ | ||
| #define __CHIP_H_ | ||
|
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| #include "sys_config.h" | ||
| #include "cmsis.h" | ||
|
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| #if defined(CHIP_LPC18XX) | ||
| #include "chip_lpc18xx.h" | ||
|
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| #elif defined(CHIP_LPC43XX) | ||
| #include "chip_lpc43xx.h" | ||
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| #else | ||
| #error CHIP_LPC18XX or CHIP_LPC43XX must be defined | ||
| #endif | ||
|
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| /* Aliasing for Chip_USB_Init */ | ||
| #define Chip_USB_Init Chip_USB0_Init | ||
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| #ifdef __cplusplus | ||
| extern "C" | ||
| { | ||
| #endif | ||
|
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| /** @ingroup CHIP_18XX_43XX_DRIVER_OPTIONS | ||
| * @{ | ||
| */ | ||
|
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| /** | ||
| * @brief System oscillator rate | ||
| * This value is defined externally to the chip layer and contains | ||
| * the value in Hz for the external oscillator for the board. If using the | ||
| * internal oscillator, this rate can be 0. | ||
| */ | ||
| extern const uint32_t OscRateIn; | ||
|
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| /** | ||
| * @brief Clock rate on the CLKIN pin | ||
| * This value is defined externally to the chip layer and contains | ||
| * the value in Hz for the CLKIN pin for the board. If this pin isn't used, | ||
| * this rate can be 0. | ||
| */ | ||
| extern const uint32_t ExtRateIn; | ||
|
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| /** | ||
| * @} | ||
| */ | ||
|
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| /** @defgroup SUPPORT_18XX_43XX_FUNC CHIP: LPC18xx/43xx support functions | ||
| * @ingroup CHIP_18XX_43XX_Drivers | ||
| * @{ | ||
| */ | ||
|
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| /** | ||
| * @brief Current system clock rate, mainly used for sysTick | ||
| */ | ||
| extern uint32_t SystemCoreClock; | ||
|
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| /** | ||
| * @brief Update system core clock rate, should be called if the | ||
| * system has a clock rate change | ||
| * @return None | ||
| */ | ||
| void SystemCoreClockUpdate(void); | ||
|
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| /** | ||
| * @brief USB0 Pin and clock initialization | ||
| * Calling this function will initialize the USB0 pins and the clock | ||
| * @note This function will assume that the chip is clocked by an | ||
| * external crystal oscillator of frequency 12MHz | ||
| */ | ||
| void Chip_USB0_Init(void); | ||
|
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| /** | ||
| * @brief USB1 Pin and clock initialization | ||
| * Calling this function will initialize the USB0 pins and the clock | ||
| * @note This function will assume that the chip is clocked by an | ||
| * external crystal oscillator of frequency 12MHz | ||
| */ | ||
| void Chip_USB1_Init(void); | ||
|
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| /** | ||
| * @brief Set up and initialize hardware prior to call to main() | ||
| * @return None | ||
| * @note Chip_SystemInit() is called prior to the application and sets up | ||
| * system clocking prior to the application starting. | ||
| */ | ||
| void Chip_SystemInit(void); | ||
|
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| /** | ||
| * @brief Clock and PLL initialization based input given in @a clkin | ||
| * @param clkin : Input reference clock to PLL1 (MAINPLL) see #CHIP_CGU_CLKIN_T | ||
| * @param core_freq : Desired output frequency of the PLL1 (Base clock to CPU Core) | ||
| * @param setbase : Setup default base clock of peripherals (see notes) | ||
| * @return None | ||
| * @note This API will initialize the MAINPLL (PLL1) to the frequency given by | ||
| * @a core_freq, and will use this PLL's output as the base clock for CPU | ||
| * Core. If @a clkin is #CLKIN_CRYSTAL then External Crystal Oscillator | ||
| * of frequency 12MHz will be used as the input reference clock to PLL1.<br> | ||
| * Parameter @a setbase if true will set APB[1,3], SSP[0,1], UART[0,1,2,3], | ||
| * SPI base clocks to MAINPLL's output clock. If @a setbase is false then | ||
| * the base clock settings for the peripherals will not be modified, only | ||
| * CPU Core's base clock will be updated to use clock generated by PLL1. | ||
| */ | ||
| void Chip_SetupCoreClock(CHIP_CGU_CLKIN_T clkin, uint32_t core_freq, bool setbase); | ||
|
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| /** | ||
| * @brief Clock and PLL initialization based on the external oscillator | ||
| * @return None | ||
| * @note This API will initialize the MAINPLL (PLL1) to the maximum | ||
| * frequency (180MHz[LPC18xx] or 204MHz[LPC43xx]) and uses this | ||
| * PLL's output as the base clock for CPU Core. External Crystal Oscillator | ||
| * of frequency 12MHz will be used as the input reference clock to PLL1. | ||
| */ | ||
| void Chip_SetupXtalClocking(void); | ||
|
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| /** | ||
| * @brief Clock and PLL initialization based on the internal oscillator | ||
| * @return None | ||
| * @note This API will initialize the MAINPLL (PLL1) to the maximum | ||
| * frequency (180MHz[LPC18xx] or 204MHz[LPC43xx]) and uses this | ||
| * PLL's output as the base clock for CPU Core. Internal RC Oscillator | ||
| * will be used as the input reference clock to PLL1. | ||
| */ | ||
| void Chip_SetupIrcClocking(void); | ||
|
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| /** | ||
| * @} | ||
| */ | ||
|
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| #ifdef __cplusplus | ||
| } | ||
| #endif | ||
|
|
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| #endif /* __CHIP_H_ */ |
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